Many 8- and 16-bit microcontrollers have difficulties to deliver the performance and functionality requirements of today’s embedded applications. However the migration to 32-bit processor cores is not necessarily the ideal solution. An efficient 8-bit CPU combined with advanced peripherals, innovative functions and extremely low power can deliver the best combination for many modern applications.

Most 8-bit architectures were developed before the emergence of high-level languages such as C. The instruction set was made for assembler, and the CPUs lack key functionality such as 16-bit arithmetic support, conditional jumps and memory pointers. Many of these architectures require several clock cycles per instruction, limiting the available MIPS at a given frequency. Some of them have reduced the clock division and increased frequency, but the theoretical MIPS are not efficiently available. Another issue is the lack of support for large memory sizes that are required in today’s applications.

To solve older CPU architectures inability to meet market needs, many vendors promote 32-bit solutions. This is great for applications that need 32-bit processing power, but many designers switch to 32-bit for the wrong reasons. Solving the 8/16-bit microcontroller limitations with a 32-bit MCU comes at a high price. A 32-bit CPU contains significantly more digital logic than any 8/16-bit CPU and use more aggressive process technologies than 8/16-bit MCUs. This increases the maximum speed and reduces the size of digital logic, but it also increases the static power consumption dramatically. For many battery powered or energy critical applications, a transition from 8/16-bit to 32-bit is not possible. High precision analog peripherals, high EMC tolerance, high I/O drive strength, external and internal oscillator oscillator options and low voltage detectors are essential for embedded applications and not easy to achieve with aggressive processes.

System performance is not just a function of MIPS, and a higher clock rate does not always solve the system performance problem. Performance is also a function of how efficiently those MIPS are used. In interrupt-driven or communication-intensive applications, better system performance is more likely to be achieved by off-loading data transfer and interrupt handling functions from the CPU and at the same time provide extra communication channels to avoid bottlenecks.

This is the approach used by Atmel®’s new family of ultra low power AVR® XMEGA™ microcontrollers. With true 1.6V operation and 2nd generation of picoPower™ technology, the XMEGA achieves industry-best low power characteristics while offering a single-cycle 32 MHz RISC CPU and significant improvements including a DMA and an innovative Event System.

DMA on all peripherals saves MIPS
The XMEGA has a 4 channel DMA Controller, and it is one of the few 8/16-bit MCUs on the market with DMA. Without using the CPU, data can be moved from a peripheral register to internal or external SRAM, between SRAM locations, and even between peripheral registers directly. The DMA can transmit from 1 byte to 16 Mbytes in a single transfer. The large data transfer size is possible due to the simple linear data memory address space in the AVR, and auto increment/decrement and reload features in the DMA controller.

Event System avoids latency and saves even more MIPS
Like a reflex in the human body the innovative XMEGA Event System enables inter-peripheral communication without CPU or DMA usage. Events are routed between peripherals through a dedicated network outside the CPU, data bus and DMA controller. The Event System enables the possibility for a change of state in one peripheral to automatically trigger actions in other peripherals. This is extremely powerful as it allows for autonomous and predictable control of peripherals without using any interrupts or CPU resources. Which event should trigger what event action is fully configurable and up to the designer to decide. The configuration can be kept static and locked, or be dynamic and change during various stages of the application execution. The response time for the Event System will never be more than 2 clock cycles of the I/O clock, shorter than any interrupt response time in the industry today.

Contact Information

Atmel Corporation

2325 Orchard Parkway
San Jose, CA, 95131
USA

tele: 408.441.0311
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www.atmel.com/avr/