MEMS and ASIC Design: How the Gap Can Narrow
As the MEMS ecosystem matures, what role will foundries play in its success?
The occasion of the 2016 MEMS Executive Congress made for a good opportunity to meet with Dr. Stephen R. Breit, VP Engineering at Coventor, a MEMS design automation firm. Breit prefaced our interview by noting his company’s concern with, and work toward, overcoming the ASIC design/MEMS design divide. “We were ahead of the industry in that we have been focused for years on bridging that gap,” Breit told EECatalog, “but the industry is now catching up with us and realizing that gap exists.” Breit also spoke about foundries’ motivations vis-à-vis MEMS, the elements found in a successful design kit, and which decisions support More than Moore—among other topics. Edited excerpts of the interview follow.
EECatalog: Why does the gap between MEMS design and ASIC design exist and why is it important to solve it?
Stephen Breit, Coventor: MEMS designers typically work in MATLAB and Finite Element tools. For ASIC designers, Cadence Virtuoso is generally the most common choice for designing analog mixed signal, that is where MEMS meets the electronics. It’s important to close the gap because, increasingly, integrated device manufacturers [IDMs] are interested in making the flow between those two design groups faster. The industry is getting more competitive, the design cycle between MEMS and ASIC must get faster, and we have a unique solution for that.
EECatalog: In addition to the increased interest IDMs are demonstrating in faster design flow, what other new developments should our readers be aware of?
Breit, Coventor: With the maturing of the MEMS industry and ecosystem, the equipment and design tools are enabling newcomers to [join the MEMS industry] with a lot less time and effort than the pioneers needed. [The pioneers] spent decades in some cases bringing MEMS to market. CMOS foundries worldwide are getting interested in MEMS, and they have multiple motivations. Some of them have announced their plans; others have not made their plans public.
And what they want to do is replicate the model that worked so well in CMOS, where foundries had design kits, developed in collaboration with design tool vendors in some case, that they could provide to their fabless customers to create new systems. Coventor has been working with X-FAB Semiconductor over the last three years through programs in Europe to develop a design kit with X-FAB for an inertial sensor technology platform.
The design kit will come out soon, and together with X-FAB and Cadence we’ve announced a worldwide MEMS design contest based on this design kit from X-FAB and tools from Coventor and Cadence that will be available to contestants to create and innovate MEMS-enabled systems.
We are seeing strong interest from other foundries to do that kind of approach—this design kit approach. It has been talked about for years, but it is finally becoming a reality.
EECatalog: How do you create the ideal design kit?
Breit, Coventor: Underneath that question is the question, “What is a design kit?”, and that is one of the things we are working out as we work with the foundries. More important, I think, for the foundries is: “Who are their customers who are going to use the design kit?” That is still evolving, but I believe there are two audiences: one, the people who want this proven MEMS technology platform and want to design their own MEMS, and two, systems houses that are already using the foundry to do ASICs and want to add some MEMS sensors to a system. And the latter case is more likely to be successful because it will not require as much MEMS expertise.
To be successful, the foundry needs some ready-to-go configurable MEMS design. So let’s say that it’s a pressure sensor for which the foundry’s customer could configure a range of sensitivity—certain high-level specs for it. Yet the customer isn’t necessarily going to become an expert in MEMS design. That will remain a more specialized domain.
The foundry must enable that customer to put a MEMS pressure sensor in their system design, which often occurs in a Mathworks MATLAB and SimuLink environment as well as an analog/mixed-signal environment from Cadence. The foundry customer needs a block for the Mathworks Simulink environment. A block for Cadence circuit schematics is also required. And then [that foundry customer] must be able to export layout from those design tools, which is then going to go through the same flow that happens today in CMOS with layout versus schematic tools, parasitic extraction, and [design rule checking] DRC.
Together with Cadence and X-FAB as well as other foundries, we are working on flow: a reference flow that the foundry’s customer will use; reference IP, which allows foundries to say, “Here’s a complete pressure sensor design.” You’ll need to design the interconnect between that and the CMOS, but you will not need to become immersed in the details of that device design, any more than you would be involved with transistor details. It’s no longer a world where the foundry customer is going to hear from the foundry, “Design any MEMS you want, and then send it back to us,” because that model is probably not going to be as beneficial to the foundries in growing their business.
Back to your question, “What is the ideal design kit?” it is one that enables them to function at that higher level efficiently. The design kit includes, if not the device model itself, a means to customize the sensor IP, create a model that goes into their circuit schematics, and go off and design the system.
EECatalog: What might the use case look like for the successful ASIC-MEMS design flow you have been describing?
Breit, Coventor: Suppose you wanted to do a design for an accelerometer, and you have some form factor you are going into, a wearable, let’s say (Figure 1). You need a two-axis accelerometer. You need a microcontroller. You need memory. You need wireless. You could go out and buy that individual two-axis accelerometer, but you would blow your form factor budget were you to do that. To meet your form factor specs, you have to put that all those pieces into a system-in-package.
So you’ll want to buy the accelerometer die, maybe it’s already capped, but you’ll want to design that system-in-package, and you’ll want to design the ASIC because you have very low power requirements and you think you can do better on that. Next, you take that accelerometer from the foundry, which will have a reference design for you adjusted to your particular sensitivity requirements. Then you design the ASIC and the rest of the system around that using blocks.
You figure out, as somebody who is creating a wearable device, to which parts of it you add value and to which parts of it you just use other people’s designs or off-the-shelf die. The foundry will supply that MEMS die, maybe capped, the CMOS die that you designed, and some other dies that are off-the-shelf or custom-made for you. The foundry will help you get it packaged with an [Outsourced Semiconductor Assembly and Test] OSAT vendor. By doing it with that degree of flexibility and integrating it at the package level, it gets you to the power requirements, performance requirements, and size requirements to enable some market.
EECatalog: Is there a particular hurdle you’d like to see addressed?
Breit, Coventor: One of the biggest impediments concerns material properties. With silicon wafers and typical material you deposit on silicon, those are pretty well characterized at this point. But for less commonly used materials, and polymers, the fundamental properties of those materials has to be something that each company has to worry about. Establishing a common data base of those materials would be beneficial. The data base could include either properties of materials or (probably more realistically), standard methods for measuring those properties, because those properties can change depending on the fabrication process. And that often is a gating issue in the accuracy of our simulations. If you don’t start with accurate characterization of the material properties, the simulation values and the predictive behavior is going to be off.
One of the benefits the foundry model can bring to the problem I have just described is for the foundries to characterize materials and embed those characterized materials in their product development kits—that is what they can offer that is not happening now. For the IDMs, the integrated device manufacturers, now, they’ve done that work, they don’t want to share it because they consider that part of their IP.
The market will probably force some of that because [of] the drive to get things packaged more densely. For a long time, we have benefitted from Moore’s Law, which got us double the density in transistors every two years and all the benefits that provided. More than Moore is about the benefits of other integration, not necessarily at the die level, but at the package level. Package-level integration is the way to get the low hanging fruit now [in the time of] More than Moore, and that means if you are an existing IDM, you put more and more stuff into your packaged component, or, your business model changes and you are selling die, not a packaged component. And somebody else is putting that together into a system. This is going to evolve over the next decade, and certainly over the next five years—pressure to integrate at the package level is going to change the business models for some of the IDMs and force some of the standardization.