Simplifying Clock Generation



Reduce Cost and PCB Footprint with Phase-Locked Loop-Based Frequency Translator ICs

Phase-Locked Loop (PLL) based frequency translator ICs, like our PL611s-02, PL613-21 and others, can be driven from a single frequency-reference source to generate the multiple frequencies required in a complex clock tree. This eliminates the need for multiple independent frequency references, saving cost and board space. Most often these devices are offered as programmable integer-N PLL ICs.
The functional block diagram of an integer-N PLL is shown in Figure 1. The input frequency to the PLL IC (fIN in the diagram) can be from a crystal, MEMS resonator, or from another frequency source that is already on the board.

A programmable integer-N PLL IC can include one or several of these PLLs. In principle, all elements of a PLL can be programmable. In practice, the programmability is usually limited to the R, N, and P counters, and sometimes the charge pump current and the loop filter parameters. In addition to elements of the PLL, some other functions of the IC can be programmable, like the strength of the output drivers (e.g. the PL671-01), or the ability to switch between various programming configurations to meet different industry standards in one clock IC (e.g. the PL613-01 and SM802XX). This article primarily focuses on the design trade-offs related to R, N, and P counter selection for optimum performance.

The programmability is usually provided by on-chip One-Time Programmable (OTP) memory. Programming software like the Microchip ClockWorks® Configurator is available to assist you in configuring/programming the IC at the sample stage. Using this tool, you only need to provide the desired input and target output frequencies, power supply information (1.8V, 2.5V, 3.3V), the output driver strength, pin configuration, etc., to program the clock IC. Some devices, like the SM802XX and SM803XX series, allow some of the IC to be reconfigured on the fly (during operation) using the SPI interface, for example.

Usually the output frequency is set by the target application. There is some freedom for setting the input frequency, but in many cases it is also set by the application. The PLL converts the input frequency (fIN) to the output frequency (fOUT ). The integer PLL does the conversion with some limitations. You will need to take these limitations into account when you specify the tolerance of the output frequency of the PLL. The equation for the output frequency of the integer-N PLL demonstrates the nature of these limitations:
Simplifying-Clock-Generation-Equation-1

The output frequency can only take discrete values. If the ratio between fIN and fOUT is an irrational number, the integer-N PLL will have to approximate this number by using a rational number. At first glance, it appears that this is not a problem because you can get close to fOUT by increasing N, P, and R. However, it turns out that there are limitations on the values of dividers in the integer-N PLL. Some of these limitations are apparent. Counters have only a limited number of bits and the Voltage-Controlled Oscillator (VCO) frequency, which is directly related to the values of counters, has low and high limits. Some of the limitations are not apparent, but they are related to the PLL being a feedback system that can be unstable with some combination of divider values. Here are some factors to consider:

The N counter value is limited by the PLL stability. If it is too large the phase margin of the PLL becomes too low and eventually the PLL becomes unstable. The higher the value of N, the lower the PLL bandwidth. Low phase margin, in addition to impairing PLL stability, leads to jitter peaking in the PLL.

A phase locked loop with a charge pump phase detector has a low limit for the phase detector sampling frequency (fR). The phase detector sampling frequency should be at least 10 times higher than the PLL open loop unity gain bandwidth.

Both of these factors limit the usable values of N, which makes approximation of the specified output frequency by the PLL more difficult. This leads to the main design trade-off of programmable integer-N PLLs: the specification of fOUT frequency tolerance should be as wide as possible. If you specify the output frequency very tight and your input and output frequencies are not related as simple integer numbers—for example 25 MHz in, 125 MHz out—you can get a PLL that will have parameters close to the limits of stability. In some cases the output frequency may not be able to be synthesized with the specified accuracy. If you can select the input frequency, choose one that offers a simple the multiplication ratio. If you need a 155.52 MHz output, select an integer-related input frequency such as 19.44 MHz or 38.88 MHz.

Simplifying-Clock-Generation-Equation-2

table

Figure 1: Phase Detector Frequency in Relation to the N Counter

To illustrate the dependence of PLL parameters on synthesis error, in this example we will generate a 24.576 MHz output from 25 MHz input. We will assume that the maximum VCO frequency of our PLL IC is at least 500 MHz and calculate the N counter value and the phase detector frequency (fR) for synthesis errors of less than 100 ppm of the specified frequency. The synthesis error is:

When the synthesis error is –86 ppm, the PLL bandwidth (~fR/10) could be as wide as 220 kHz. If the error is specified as 20 ppm, the PLL bandwidth cannot be more than about 80 kHz.

You should pick the highest value of synthesis error that your system can tolerate. If the acceptable synthesis error is not specified, the programmer software will try to synthesize the output frequency with minimum error that is achievable from a PLL stability point of view. Note that the synthesis error will be in addition to the accuracy of the input source.

The selection of counter values also affects the PLL’s phase noise. A PLL is a low-pass filter for reference frequency phase noise and a high-pass filter for VCO phase noise. Inside the PLL bandwidth, the reference phase noise is multiplied by N and divided by R. The filtered phase noise of the VCO is divided by P at the output. The resulting phase noise at the output is a combination of all those factors. Except when the PLL is used to clean the reference, the contribution of the reference phase noise, even after multiplication, is lower than the VCO phase noise at all frequencies except very close to the carrier (referred to as ‘close-in’ phase noise). Therefore, to reduce the phase noise at the output, it is advantageous to have as wide a PLL bandwidth as possible. Since VCO phase noise is divided by P, it is preferable to run the VCO at the highest frequency possible. It should be noted that this leads to higher power consumption.

The phase noise describes the noise components of the signal in the frequency domain. The jitter describes the signal noise in the time domain. These parameters are related but their relations are complicated. In case of a PLL, the situation is even more complicated than in case of a direct crystal oscillator since, in addition to random jitter that is related to the random phase noise, the PLL generates deterministic jitter that is related to crosstalk between the PLL building blocks: VCO, phase detector, and the counters. The random part of the jitter follows the same rule as the phase noise—the wider the PLL bandwidth and the higher the VCO frequency, the better random jitter. Deterministic jitter is much more difficult to characterize. Some of it is due to the VCO control voltage (Vc) ripple at fR frequency that passes through the loop filter. This component is attenuated when fR is much higher than the PLL bandwidth, so to reduce the deterministic jitter the PLL bandwidth should be low comparing to fR. Another rule of thumb is the more dividers are involved, the more crosstalk-related deterministic jitter you will have. One of the consequences of this rule is the more PLLs are used on the chip, the more crosstalk between PLLs. From the deterministic jitter point of view, a single PLL IC will have less jitter than a multiple PLL IC. If your application is sensitive to jitter, consider using a separate PLL IC for each frequency or for the most sensitive frequencies.

Many PLL ICs have a crystal oscillator as part of the IC. These ICs usually have a reference output that is the buffered output of the crystal oscillator. Note that the reference output of a PLL IC most likely will have higher jitter due to the crosstalk from the PLL(s) operating on the same die than a stand-alone crystal oscillator. This additional jitter will be mostly deterministic in nature.

Besides other factors affecting the jitter performance, the PLL jitter is highly dependent on the R, N, and P counter selections. Therefore, the performance of a PLL IC depends on optimal selection of counter values. The jitter performance of a particular input/output frequency combination may vary from the published typical numbers. You should ask for the jitter performance of the requested samples or study the conditions (PLL configuration) in which the published jitter numbers were measured.

Since deterministic jitter depends on crosstalk, it depends on the phase relations between various intermediate frequencies existing inside the IC. Since some of these phase relations can vary from one power-up of the chip to another, the jitter can be different from one power-up of the same chip to another. The jitter can also be different if measured between the rising or the falling edges of the output waveform.

The deterministic jitter of a PLL has some properties that can be used to analyze its impact on the target system. As its name implies, it depends on the finite number of frequencies that are known or could be calculated by considering all possible mixing products of frequencies present in the PLL. The frequencies contributing to deterministic jitter can be measured by a spectrum analyzer. The peak-to-peak value of deterministic jitter is a bounded number that does not grow with the number of period measurements as a peak-to-peak random jitter value does. You should evaluate the target system in terms of how the frequencies causing the deterministic jitter will affect it. The deterministic jitter may create ‘multimodal distribution’ on the period jitter histogram. However, the multimodal distribution caused by deterministic jitter on the period jitter histograms should not prevent you from using a PLL. For example, the intermediate frequencies resulting in the deterministic jitter could be high enough to be attenuated by the internal PLL(s) of the target system.

Some PLL ICs have programmable output buffers. They allow changing the buffer strength vs. output frequency, output level, and buffer supply voltage. The rule of thumb is to use the lowest drive level your application can accept. Too high a drive level could lead to excessive EMI from the board. It can also increase crosstalk. Usually, the high drive is recommended for frequencies above 100 MHz or if the buffer supply voltage is low, for example, 1.8V.

High drive can improve the measured jitter because it reduces conversion of AM to PM at the input of the measurement equipment due to decrease of the rise and fall times.

The layout of the board with a PLL IC requires special attention to power supply pin decoupling. It was mentioned above that the crosstalk is a major contributor to the PLL jitter. Some of the crosstalk comes from inside the IC and cannot be changed. But some of the crosstalk comes from the PLL block’s interaction through the power lines. All the power pins must be decoupled with capacitors placed as close to the power pins as possible. When selecting capacitor values for decoupling, remember that a PLL is a multi-frequency system and—together with 100 MHz at the output—it can have frequencies in kHz range on chip that could modulate power supply voltage and VCO frequency and create crosstalk. If you use inductors or ferrite beads for decoupling, look for the possibility of resonances in the power supply lines. PLLs are more sensitive to decoupling than oscillator ICs and can be unstable in conditions where an oscillator IC would be stable.

As mentioned above, the programmable PLLs keep information in OTP and configure themselves during power up. They start in the unprogrammed state. The transition from unprogrammed state to the programmed state could be quite complicated when using multi-PLL ICs with several programmable banks. Because of this, the requirement of the power supply ramp for programmable PLLs is more stringent than in case of ICs with a fixed structure, such as oscillator ICs or simple pin-programmable PLLs. Usually the ramp must rise monotonically without dropouts, and there could be minimum and maximum ramp time requirements.

By following these simple design guidelines, you can use programmable PLLs to replace multiple crystals, crystal oscillators and other reference sources to simplify clock generation in a number of applications. To learn more about our products and the ClockWorks Configurator, visit our Clock Generation page. For additional information about PLL design, we recommend the following resources:
F.M. Gardner, Phaselock Techniques, 3rd ed, John Wiley, 2005.Keliu Shu, Edgar Sánchez-Sinencio, CMOS PLL Synthesizers: Analysis and Design, Springer, 2005.

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