Changes in Memory Storage Herald a Dynamic Future
Technology developments are introducing memory storage option choices. For 3D NAND in particular, there is a drive to address the challenges faced in implementing the technology in embedded applications.
Last year, Micron and Intel announced the 3D Xpoint memory, a jointly developed Storage Class Memory (SCM) that uses Phase Change Material (PCM) to store, and release, large amounts of energy. Analyst firm Yole Développement commented that this introduction marks a big comeback for PCM in the Non Volatile Memory (NVM) market, after it had lost ground to Resistive Random Access Memory (RRAM). Benefits of 3D Xpoint, says Yole, are a high density of 128-Gbit, a 20nm process node, and a 3D crosspoint structure. The analyst firm expects PCM to have the largest share of the emerging NVM market by 2021. This is partly due to the profile and strength of Intel and Micron. It even speculates that a new SCM category may be created, using 3D Xpoint in the memory hierarchy, which may eclipse sales of Dynamic Random Access Memory (DRAM).
Intel has also partnered with Micron to develop 3D NAND technology, where layers of data storage cells are stacked vertically, and claimed to produce devices with three times more storage capacity than competing NAND technologies (Figure 1).
The increased interest in SCM has come about as planar NAND Flash memory is reaching its scaling limit. Shrinking production processes do not necessarily result in cost reductions. Hence the active search for alternative technologies.
Another driving force is the increase in connected devices as well as digital services and the rise in cloud applications, all culminating in increased data.
For Rob Crooke, Senior Vice President and General Manager, Non-Volatile Memory Solutions Group, at Intel, this burgeoning market that creates increasing amounts of data is a double-edged sword. “This combination of data growth and increased computing capability is a fantastic opportunity to transform both device and cloud computing, which in turn creates a virtuous cycle of growth,” he says. “However, a key challenge lies in getting data much closer to the Central Processing Unit (CPU).”
Historically, Crooke explains, the CPU waits for data from storage, which coupled with memory capacity and its proximity to the CPU, have been design challenges, limiting performance. Larger memory capacity and faster storage, paired with cloud computing, will benefit many applications, from gaming, where play will be immersive and uninterrupted, to commerce and science. This can be automating services, or the ability to process and analyze large genetic data sets in real-time for healthcare research, he writes.
The company is already collaborating with Facebook, where the social media company is re-architecting it storage hierarchy for Intel Optane Solid State Drive (SSD) prototypes, which are based on 3D Xpoint Memory Media. Already, reports Crooke, there is an increase in the speed of movement of data between the storage device and the CPU, reducing latency by a factor of 10, and increasing throughput by a factor of three, compared to NAND SSD.
3D NAND Approaches
Taiwanese embedded Flash, SSD and DRAM module manufacturer, ATP Electronics announced new lines of M.2, mSata, SlimSata, 2.5-inch SSD, eUSB and memory cards based on 3D NAND Flash technology.
Although targeting the client and enterprise markets initially, the company describes as inevitable 3D NAND’s move to embedded design for IoT, industrial, medical, automotive, and telecom.
Typically, 3D NAND allows for higher capacities in devices and increased capacity per chip compared with 2D NAND. David Raquet, Channel Sales Manager, ATP, cites other benefits such as endurance, performance, data retention and lower cost per GByte, which make 3D NAND suitable for the embedded space. He also believes that 3D NAND will drive innovation, predicting: “3D NAND will allow for a variety of product configurations to optimize products towards individual customer requirements.”
The challenge for 3D NAND in embedded applications is the diversity of applications that require 3D NAND to be verified in different scenarios. “Extensive verification testing is required to understand the new technology’s capabilities and limitations in embedded application environments,” says Raquet. “In addition, our products are typically required to run in the end application for a longer period of time, so we need to put particular focus on longer-term reliability.”
The company’s announcement at the Flash Memory Summit 2016 also referred to its wafer packaging and testing. Raquet notes that the company has recently moved towards self-packaging, whereby it buys wafers from its suppliers that it integrates into the packages required. This not only simplifies the supply chain, he explains, but also makes the company more flexible and able to produce a wide range of products, while increasing long-term availability.
“We are currently packaging and testing 3D NAND Flash from our suppliers and expect 3D NAND to have a significant impact on future product designs,” he says.
Another partnership is that of Toshiba and SanDisk, to develop and promote Bit Column Stacked (BiCS) 3D NAND. The technology is based on a multiple-layer stacking processing.
Axel Stoermann, General Manager, Memory Technical Marketing and Application Engineer at Toshiba Electronics Europe, explains the company’s approach to 3D NAND structure. “By allowing larger lithographic processes to be used, our BiCS technology reverses the trend for die shrinking, which reduces cell-to-cell noise and interference. Consequently, both write/erase reliability and endurance and write speeds can be increased,” he says.
The company invented NAND Flash technology, says Stoermann, and operates the world’s largest, single complex, dedicated to producing NAND Flash in Yokkaichi, Japan. There, the Fab 2 focuses on 3D BiCS manufacture.
SanDisk has recently announced its 3D NAND pilot line operations and production of a 256-Gbit, three-bit-per cell (X3) chip, in conjunction with Toshiba. It is believed to be the world’s first 256-Gbit, X3 device using 48-layer BiCS technology.
“Thanks to its structure, 3D BiCS NAND is well-suited to meeting the reliability, [and] endurance data rates demanded by client and enterprise servers,” he says. He offers the example of a typical 15nm 2D NAND device, with sequential write speeds of 20 to 30-MByte per sec, compared with a 3D BiCS process, which can achieve 30 to 40-MByte per sec. “3D BiCS NAND is also suited to automotive applications that can take advantage of improved endurance, especially when used with an appropriate interface standard,” he says.
Interface selection highlights differences that are critical when applying the technology to embedded applications. There are two primary standards appropriate for NAND Flash, e-MMC (Embedded MultiMedia Card) and Universal Flash Storage (UFS). Of these, e-MMC was originally designed for consumer applications, (smartphones, tablets, servers, printers, navigation system) and some industrial and automotive applications, Stoermann says. UFS, with its Small Computer System Interface (SCSI) architecture, is more heavily focused on embedded and removable Flash storage in smartphones and tablets. “The key difference is performance,” he says. “e-MMC supports half-duplexing, meaning that the host can read and write, but not at the same time. UFS, on the other hand, supports full duplex operation. This means that UFS is well-positioned to take advantage of the capabilities of 3D NAND more fully,” he concludes.
Development continues, and Toshiba, the company that invented NAND Flash technology, Stoermann points out, is sampling the next level of 3D BiCS Flash memory, with a 64-layer device. The 64-layer structure uses three-bit per cell, which the company terms Triple Level Cell, or TLC, technology. The memory has a capacity of 256-Gbit, or 32-GByte. Mass production is scheduled to start in the first half of 2017.
Tests show that it delivers an increase of 40 percent in capacity, compared with the 48-layer device. Stoermann adds that other benefits are reduced cost-per-bit and increased manufacturability of memory capacity per silicon wafer. These are important benefits in a market preoccupied in its pursuit of increased storage for price-sensitive markets.
Caroline Hayes has been a journalist, covering the electronics sector for over 20 years. She has worked on many titles, most recently the pan-European magazine, EPN.