Archive for July, 2016

Altair Collaborates with Luxury Sports Car Maker, Ferrari, to Develop ‘Next Generation’ Vehicle Platform

Wednesday, July 27th, 2016

TROY, Mich., July 27, 2016 /PRNewswire/ — Altair has collaborated with luxury sports car maker, Ferrari, to design and engineer the company’s ‘Next Generation’ vehicle platform which will be the basis of several new flagship vehicle derivatives. The announcement signifies the strong and mutually beneficial relationship that the two companies have enjoyed since Ferrari started working with Altair over a decade ago.

To develop the Next Generation platform, Altair supplied a highly specialised group of designers and engineers working on-site at Ferrari’s vehicle development centre in Italy. The team worked alongside Ferrari’s own design, engineering and manufacturing teams.

Maximilian Szwaj, Ferrari’s Director of Innovation and BIW Development, stated, “It was important for Altair to supply both CAD and CAE expertise to facilitate tight integration particularly when packaging ideas and manufacturing process are so fluid. The speed of the optimization processes deployed were able to control the weight whilst achieving the demanding structural targets as new packaging changes were introduced. For Ferrari, the Next Generation platform is a significant engineering achievement and a symbol of our successful collaboration with Altair.”

Innovation is the driving force behind the vehicle development process at Ferrari and Altair’s team successfully utilised innovative design optimization methods (e.g. Altair’s Concept Optimization Driven Process C123), driven by the HyperWorks suite of simulation technologies. Outstanding performance is a fundamental part of Ferrari’s DNA. The Next Generation platform is 15% lighter, while enhancing the performance of crash, NVH and other critical attributes by over 20%. Altair’s solver and optimization technologies, RADIOSS and OptiStruct for crash and NVH respectively were key tools in achieving the outstanding weight and performance characteristics.

Dr Royston Jones, Exec VP European Operations & Global CTO, Altair ProductDesign, “For Ferrari to trust Altair to support the delivery of the Next Generation platform as a strategic partner was a great compliment. Ferrari provided an Innovation Environment where, together with Ferrari’s engineering team, our engineers and designers had the freedom to apply new technologies. As an innovation strategy, Ferrari encourages ideas from everywhere and our new design processes were able to rapidly assess the majority of ideas.”

“I love the Next Generation architecture, it has an organic nature, with the structure flowing smoothly from sections to joints. It’s an outcome of a massive deployment of structural optimization defining optimum material layout resulting in outstanding weight / performance characteristics. I believe it truly warrants the title of Next Generation and importantly, repays Ferrari’s trust.”

For an overview of Altair’s C123 visit www.altair.com/C123.

About Altair
Altair is focused on the development and broad application of simulation technology to synthesize and optimize designs, processes and decisions for improved business performance. Privately held with more than 2,600 employees, Altair is headquartered in Troy, Michigan, USA and operates more than 45 offices throughout 22 countries. Today, Altair serves more than 5,000 corporate clients across broad industry segments. To learn more, please visit www.altair.com.

Media Contacts:
Corporate / Americas
Biba A. Bedi
+1.757.224.0548 x 406
biba@altair.com

Europe, the Middle East and Africa
Evelyn Gebhardt
+49 6421 9684351
gebhardt@bluegecko-marketing.de

Contact Information

Altair Semiconductor

6 Ha'harash Street
P.O. Box 7158
Hod Hasharon, 45240
ISRAEL

tele: +972-74-7800800
fax: +972-9-7403049
http://www.altair-semi.com/

The Brilliant Backseat Reminder System Helps Drivers Remember Precious Cargo

Friday, July 22nd, 2016

Rear View Safety, the industry leader in the sales and distribution of backup camera systems, as well as a strong and dedicated road safety advocate, is proud to announce the release of the RVS-BLB Brilliant Backseat Reminder System. The product is designed from the ground up to remind drivers to take children, pets, or valuables out of the backseat of the car.

On average, 37 children lose their lives every year from heatstroke after being left in hot cars. 661 children have died from heatstroke in an 18 year period. Of those 661, 54% were “forgotten” by their caregiver. Even with the windows cracked, the temperature inside of a car can reach 125 degrees in a matter of minutes. Death occurs when core body temperature reaches 113 degrees. Pets left in backseats are also at risk for heatstroke. These statistics bring to light a very serious issue that needs to be addressed and solved, which is precisely what the Brilliant Backseat Reminder System is designed to do.

The beauty of the Brilliant Backseat Reminder System is its simplicity. When the backdoor is opened before the vehicle is started, the system recognizes that something, or someone, was put in the rear of the car. When the driver arrives at the destination and leaves the vehicle, the RVS-BLB actives a moderate audio alarm to remind them about the cargo. If this alarm is not turned off in 40 seconds, the system activates the vehicle’s horn to draw attention. The Brilliant Backseat Reminder System saves lives, giving the driver peace of mind in a busy and ever changing world.

To find out additional information about the RVS-BLB Brilliant Backseat Reminder System, or to learn more Rear View Safety – please visit the company’s official website at http://www.rearviewsafety.com/ or call 800-764-1028 today.

Rear View Safety is not a stranger to the world of safety enhancing products for drivers and vehicles of all types. Recently they introduced GoVue, the first back up camera smartphone app for the popular iOS and Android operating systems. Once the smartphone and camera system are connected via a short-range Wi-Fi network, video information from the rear of the vehicle is transmitted to the smartphone in real time. This eliminates the need for a primary monitor to be installed into the dashboard of the vehicle. The GoVue back up camera application for iOS and Android devices is currently available for free download in the Google Play Store and the iTunes App Store.

Rear View Safety has long been a leader in vehicle safety solutions. The commercial backup camera provider is also available on Facebook, Twitter, LinkedIn, and maintains a Road Safety Resource site.

Contact Information

Rear View Safety Inc.

1797 Atlantic Ave
Brooklyn, NY , 11233

tele: (800) 764-1028
fax: (800) 764-1028
info@rearviewsafety.com
http://www.rearviewsafety.com/

u-blox introduces automotive grade qualified positioning and connectivity modules

Wednesday, July 20th, 2016

Automotive qualified modules follow 0-ppm failure rate program and are manufactured in an ISO/TS 16949 certified facility

Thalwil, Switzerland – July 20, 2016 – u-blox (SIX:UBXN), a global leader in wireless and positioning modules and chips, today announced the expansion of its product offering with automotive qualified product variants added to their range of positioning and cellular wireless connectivity modules. The additions comprise the NEO-M8Q-01A and NEO-M8L-01A, and respectively the SARA-G350-02A and LISA-U201-03A. Manufactured according to the ISO/TS 16949 automotive supply chain quality management standard, the modules are thoroughly tested with an extended qualification process aimed at achieving the lowest level of failure rates. Leveraging the early production experience of tens of millions of professional grade modules, u-blox automotive grade modules consistently reach excellent quality levels. With long product life cycle characteristics, u-blox manufacturing management includes industry recognized processes such as automotive PCN, PPAP, and 8D failure reporting.

The NEO-M8Q-01A and the NEO-M8L-01A positioning modules provide concurrent reception of GPS, GLONASS, Beidou, and Galileo. The NEO-M8L-01A is ideally suited to providing 100% dead reckoning positioning coverage even in areas of weak signal such as in tunnels or multi-story car parks or those experiencing poor signal quality such as caused by multi-path reflections. This module is qualified to operate in the -40 to +85 degrees temperature range and the NEO-M8Q-01 GNSS module is the first GNSS module able to operate across the extended automotive temperature range from -40 to + 105 degrees Celsius.

The SARA-G350-02A is a quad-band GSM/GPRS data and voice connectivity module that is certified for provisioning global connectivity. The LISA-U201-03A also provides global connectivity with 5 HSPA bands, with data rates up to 7.2 Mbps. Both these modules accommodate the automotive operating temperature range of – 40 to + 85 degrees Celsius, have a compact footprint and consume very little power.

With these product additions, u-blox is able to supply a complete range of automotive grade connectivity and positioning modules for use in navigation systems, telematics, e-Call, road tolling, and ADAS applications. The recently announced V2X and Wi-Fi modules THEO, EMMY, and ELLA complete this portfolio.

Samples are available in August and full production will commence in September 2016.

About u-blox
Swiss u-blox (SIX:UBXN) is a global leader in wireless and positioning semiconductors and modules for the automotive, industrial and consumer markets. Our solutions enable people, vehicles and machines to locate their exact position and communicate wirelessly over cellular and short range networks. With a broad portfolio of chips, modules and software solutions, u-blox is uniquely positioned to empower OEMs to develop innovative solutions for the Internet of Things, quickly and cost-effectively. With headquarters in Thalwil, Switzerland, u-blox is globally present with offices in Europe, Asia and the USA.
(www.u-blox.com)

Find us on LinkedIn, Twitter @ublox, YouTube, Facebook and Google+

u-blox contact:
Natacha Seitz, Senior Professional PR
Tel. +41 44 722 7388
natacha.seitz@u-blox.com

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Wire-Free Charging to Revolutionize Device Usage Once the Industry Overcomes Its Hurdles

Monday, July 18th, 2016

Scottsdale, Arizona – 18 Jul 2016 – Wireless charging promises to radically change the market landscape, particularly if long-range, wire-free technologies meet key milestones. Imagine a world in which people will never again have to make a conscious effort to charge their devices; they will charge as consumers go about their daily lives, without being plugged in or resting on a charging pad. This is the industry’s vision for long-range, wire-free charging, but hurdles stand in the way. And even if obstacles, like regulatory approval, are overcome, ABI Research predicts that it will likely be years before these technologies become a mainstream solution.

“Select retailers, auto manufacturers, enterprises, and mobile leaders like Samsung and Apple are moving wireless charging forward by integrating inductive charging into smartphones and wearables,” says Michael Inouye, Principal Analyst at ABI Research. “But most wire-free charging technologies still need to meet regulatory approval, which could significantly delay product launches or even derail any momentum garnered thus far.”

The standards battle for short-range, inductive charging, and the early steps to resonant charging between the Wireless Power Consortium (Qi branded) and AirFuel is largely mitigated by multi-mode receivers, which are already leading shipments from market leaders like IDT. To supplement wireless charging in the meantime, numerous companies are advancing today’s battery technology through enhancements to existing Li-ion technology. Some, like portable fuel cell leader MyFC, even offer end users added flexibility and portability when charging their devices through methods like off-grid charging. But as wireless charging steps to the forefront of this market, the competitive landscape will focus less on competing technologies and more on the growing number of applications and use cases.

“Inductive and resonant charging remain the best wireless charging options for now, with shipments clearing one billion by 2019,” concludes Inouye. “Wire-free charging still has many questions to answer in the market. Energous looks like it will be the first company to start commercializing its claims, as it already secured the early critical licensees necessary to bring the products to market. It will debut short-range charging products that targets wearables to help seed the market before it expands to longer range solutions.”

These findings are from ABI Research’s Battery, Fuel Cell, and EH. This report is part of the company’s Wearables & Devices sector, which includes research, data, and analyst insights.

Contact Information

PCI Express Passes Other Standards Found in Automobile Entertainment Systems

Thursday, July 7th, 2016

Move over CANbus, PCI Express is the latest communications technology found in automotive infotainment.

Regarding “car tech,” we take for granted that every window motor, headlamp and trunk release has its own MCU; there might be a hundred MCUs and sensors interconnected via networks in the modern car (Figure 1). Yet the hotter topic for automotive designers now is the car’s “connectedness” to the Internet, advanced safety features like lane departure or self-parking, and in-vehicle infotainment (IVI).

Figure 1:  Today’s automobiles are loaded with networks, cameras, and the all-important center console in-vehicle infotainment (IVI) system.

Figure 1: Today’s automobiles are loaded with networks, cameras, and the all-important center console in-vehicle infotainment (IVI) system.

The center console IVI system is a consumer must-have item and differentiates car brands. High-end auto manufacturers offer more features—such as front-mounted radar or 360-degree camera vision—but even the lower tier brands include back-up cameras, smartphone integration (and Google’s Android Auto or Apple’s CarPlay) along with Bluetooth and smart device charging (Figure 2).

Figure 2: Android Auto. (Courtesy: http://www.android.com/auto and YouTube.com )

Figure 2: Android Auto. (Courtesy: http://www.android.com/auto and YouTube.com )

The IVI system block diagram reveals sensors and graphics, media processors, packet-based networks, and PCI Express peripherals. The IVI console is actually a collection of many embedded systems that rely on the efficiency of the PCIe interface.

Yet cars are also unique. Designers need to account for 10-year life cycle requirements, wicked EMI mitigation and “dirty” power, plus all manner of temperature extremes in a moist and corrosive environment.  Architecting—and spec’ing components for today’s connected car—are a designer’s challenge.

Connected Cars Modify IVI Architecture

Within just a few years, the majority of automobiles will be “connected”—to the Internet, to the occupants’ mobile devices, and to each other and the road’s infrastructure. Data by BI Intelligence shows about 75% of the cars sold by 2020 will be connected (Figure 3). This trend has forced a rethinking of the car’s architecture by separating the “telematics” processing from the IVI system, requiring a more complex IVI design.

Figure 3: The market is trending towards more cars being connected via cellular modem.

Figure 3: The market is trending towards more cars being connected via cellular modem.

While it was once thought the IVI processor would be the car’s primary CPU controlling all the other MCUs via CANbus network—the telematics with 4G LTE cellular modem block will instead connect to the IVI system via automotive-grade high-speed Ethernet AVB. This frees the IVI system to have more local processing, interface to a variety of sensors, and be a connected yet sophisticated embedded system of systems (Figure 4). Key technologies needed in this architecture are packet switches and bridges, along with timing devices. Let’s examine each briefly.

image001(1)

Figure 4: The standalone, yet networked, IVI embedded system. Each functional block represents a separate sub-system.

Life in the Fast Lane: Packet Switches

Switches are increasingly common in embedded systems for one key reason: the limited number of I/O options available on high-density SoCs. When pins are at a premium, either because they are needed for other I/O or to keep costs down, something’s got to give.

The packet switch is differentiated by moving data between the ports while maintaining the original source packet formatting. Figure 5 shows this put to practice in our notional IVI system.

ReDeiver in Automotive App

Figure 5: Packet switches used in an IVI system; the switches for PCIe and USB increase fanout from processors with limited I/O and/or pins.

Shown in Figure 5 is a notional IVI system with center console (instrument panel can also be included), and USB entertainment and storage peripherals. Shown is a 4-port PCIe (packet) switch, which is used to increase the SoC’s PCIe fanout from a single port to three downstream PCIe ports. Without this switch, no additional PCIe devices could attach to the IVI’s SoC processor.

The packet switch in the telematics module is always “on” as it is used for entry, remote start and other functions utilizing wireless protocols. Therefore, having a packet switch with very low standby power is critical, especially for the telematics module, and is a power-saving feature for the infotainment module.  Pericom’s small 3 (PI7C9X2G304SL) and 4 port PCIe GEN2 packet switches (PI7C9X2G404EL) can provide very low standby power to specifically address these applications.

One PCIe switch example from industry is the Pericom PI7C9X2G404EL 4-port, 4-lane PCIe 2.0 packet switch. A single x1 PCIe lane connects to the host controller, while three x1 Gen 2 ports connect to endpoints. More than a simple switch, the device has a low 150ns “non-blocking” latency between ports but also allows “store and forward” capabilities to buffer packets. Link power management per the PCI Express spec assures interoperability, and the device is available from -40 ºC to +85 ºC and in automotive versions starting 3QCy16. Pericom will have AECQ qualified small packet switches available in 3QCY16.

Intelligence Right at the PCI Express Switch

One other interesting feature about the Pericom PI7C9X2G404EL 4-port, 4-lane packet switch is that it supports Single Root I/O Virtualization (SR-IOV) address translation. This is part of the PCI Express specification that defines a standardized mechanism to create natively shared devices when virtual machines (VM) are employed. Although Figure 5 doesn’t reflect a VM architecture, it is quite possible that such an architecture would be employed in an IVI system if the IVI processor was also responsible for some of the car’s telematics functions. In that case, partitioned virtual environments would be used for security and safety critical operations.

Figure 6 shows that PCI Express packet switches are also needed for the IVI system but outside of it for dealing with remote sensors. In this diagram, the advanced driver assistance system (ADAS) sub-system connects with IP-based cameras using Gigabit Ethernet. The GigE controller is bridged to PCIe, which is then packet switched to the ADAS processor through a Pericom PI7C9X2G304SLBQ (the Q meaning AECQ qualified); the other port connects to a PCIe Wi-Fi controller.

Figure 6: Example ADAS safety system using a PCIe packet switch for moving IP data into the IVI main system.

Figure 6: Example ADAS safety system using a PCIe packet switch for moving IP data into the IVI main system.

This PCIe packet switch is similar to the one shown in Figure 5; however, it has 3 ports (typically one in and two out) but one port can be configured as a PCIe x2 lane port. This provides twice the data throughput on this port—useful to service two data-hungry downstream ports like Wi-Fi and GigE. To save power, downstream ports are set to idle.

Plenty of Time

Figure 7 highlights the timing blocks typical in an IVI system, which is a bit more detail than was shown earlier in our notional IVI system in Figure 5. Even though the IVI embedded system is in a car, it still requires precision clocks and timing sources for the digital components. Here, the emphasis is on accuracy over a wide temperature along with the ability to clock multiple controllers with one clock source.

The concept of “one to many” is made clear by referring back to Figure 6 where a single clock generator is capable of meeting the timing for both the SoC and the PCI Express packet switch. The device shown, PI6C557-03AQ PCIe 2.0 clock generator by Pericom, runs on 3.3VDC and operates over a wide AEC-Q100 qualified industrial/automotive temperature range—probably the most critical requirement for a timing device.

In this application, output frequencies of 25MHz, 100MHz, 125MHz and 200MHz provide flexibility to drive many kinds of PCIe peripherals and controllers. The onboard PLL remains steady over temperature and merely requires an equally steady 25MHz crystal oscillator as shown.

In an automotive environment that is sensitive to electromagnetic interference, Pericom’s PCIe clock generators are capable of providing spread spectrum output clock signals to help lower EMI from the high frequency clocks. The various spread spectrum settings of 0%, +0.25%, -0.5%, and -0.75% are available for system designers to select and change to ensure that their design passes the strict EMI requirements of the automotive industry without sacrificing the performance of the PCIe link.

Figure7_newer

Figure 7: Clock/timing sources for IVI systems.

On the Move

The world has always loved the automobile as a way to get places quickly, a means of independence, and increasingly as a personal space to escape. But in today’s connected world where the Internet is the backbone of modern commerce, the connected car demands more sophistication from the center console IVI system.

Yet even with enhanced graphics, smartphone connectivity, and high-density SoC processors, the IVI system fundamentally remains an embedded system. And, as with all high-speed embedded systems, engineers must be aware of packet switches and bridges and timing solutions, and remain vigilant in dealing with high-speed signal integrity challenges.

This article was sponsored by Pericom Semiconductor now a part of Diodes, Incorporated.

Progress in the Air: Q&A with Cypress Semiconductor

Thursday, July 7th, 2016

Firmware over-the-air updates and the growing importance of software in the vehicle.

Sven-Natus-CypressSven Natus, Head of Automotive Business Unit Americas at Cypress Semiconductor, believes “immediately” should mean “immediately.” And that’s a problem for traditional flash technology, as Sven explained during our recent EECatalog interview about how Cypress is working to make over-the-air updates something automotive OEMs can rely on. Edited excerpts from the interview follow.

EECatalog: Over-the-air updates are getting a lot of attention. Is the semiconductor industry overall prepared to support the growing demand for such things as firmware over-the-air (FOTA) updates?

Sven Natus, Cypress Semiconductor: No, one reason being that today flash macros allow you to either read the memory or to write it, but not to do both [actions] at the same time. So, based on Cypress having a broad portfolio of products, what we’ve proposed to customers and what we successfully demonstrated to all the major automotive OEMs, is that the high bandwidth that our HyperFlash memory (Figure 1) comes with permits us to execute code out of the external flash—this is the key feature that we need here—the execution of code without significant drop in performance for the microcontroller. HyperFlash allows us to do that. We are also able to connect two HyperFlash Memories to our Traveo microcontroller.

Figure 1: Bandwidth is key for achieving the execution of code without significant drop in performance for the microcontroller.

Figure 1: Bandwidth is key for achieving the execution of code without significant drop in performance for the microcontroller.

These two HyperFlash memories are completely independent of one another. So I can execute software out of one type of flash memory, while at the same time I can program the second type of flash memory with an updated version of the software. This is very attractive, because with this ability to execute and provide updates in the background there is no interruption in ECU [Electronic Control Unit] operation. A second advantage is that if there is a problem with the update, it’s possible to go back to the previous version because the HyperFlash memories always hold two complete software versions simultaneously.

EECatalog: Why is over-the-air functionality becoming popular?

Natus, Cypress Semiconductor: Over-the-air technology makes it possible to prevent numerous recalls on vehicles because now you can push updates into the vehicle remotely, saving a significant amount of money. And given the fact that software is becoming a more and more important part of the vehicle and also a more dominant part of the vehicle compared to the actual electronics, OTA helps to reduce the quality costs for the OEM because many of the recalls are software-related.

Second, OTA software updates can provide new features and that [functionality] could be combined with on demand features. You can imagine the user choosing from a menu of features he or she would like in the vehicle, and, as long as it is a purely software-enabled feature, it can be downloaded.

EECatalog: You’re seeing software as gaining in importance?

Natus, Cypress Semiconductor: Yes, software is becoming a more and more important part of the vehicle, and we also see that the time to market is getting shorter. Vehicles are getting more complex.

Over the last few years Cypress has become more involved in software development, and today software is a key aspect of our business. The software products that go along with our semiconductor solutions make it easier for our customers because the more we can abstract the hardware level, the easier it will be for customers to use our solutions. They won’t have to deal with a multi-thousand page hardware manual in order to understand how the semiconductor works.

EECatalog: How soon will we see vehicles ready for firmware over-the-air updates?

Natus, Cypress Semiconductor: We are already working with OEMs on these concepts—this is something we are actively pursuing today. Given all the lead time [required] for development of vehicles, which, typically, once we start working with the Tier 1’s it’s around three years until the sales orders, so by 2019 we’ll see these vehicles coming out.

EECatalog: What should we expect to see as autonomous vehicle development gets under way?

Natus, Cypress Semiconductor: We will see lots of requirements with regard to data storage—just think about the liability in case of an accident—how do you prove that your vehicle did not do anything wrong? So in that case you need to have a solution that permits you to store all kinds of sensor data real time and permanently—immediately.

And immediately means immediately. Typical flash technology requires some time to be programmed and sometimes, in the case of an accident, you might not even have that time. To address that Cypress is offering F-RAM technology, which permits you to write it immediately as RAM, but it is a nonvolatile RAM, so it can store data instantaneously—this is an important aspect going forward when we look at storing data in the vehicle.

What is also important to know about the F-RAM is that the write cycles go in dimensions of 1014, so a trillion write cycles, which is more than you would ever need for the lifetime of the vehicle. It’s highly reliable technology.

EECatalog: What are some other ways Cypress is preparing for the embedded automotive electronics world ahead?

Natus, Cypress Semiconductor: The recent acquisition of Broadcom’s IoT wireless division enhances our portfolio with wireless technology. With Bluetooth’s low energy connectivity in our portfolio, plus the full Bluetooth stack as well as WiFi technology, will be of great importance, not only for connectivity inside the vehicle, but also for Vehicle-to-Infrastructure and Vehicle-to-Vehicle communication.

At this time we are trying to expand our portfolio strategically. We don’t want to be a traditional semiconductor supplier that provides you with a single chip. We really try to provide our customers with complete solutions. We are successfully doing that today in some markets, and we want to extend these capabilities to other arenas.

EECatalog: Are there more items on the “shopping list”?

Natus, Cypress Semiconductor: Certainly given the complexity of a vehicle, there are parts of the puzzle that are missing with Cypress to achieve that goal. On the other hand, we don’t want to become a Tier 1 or compete with our customers, but you can expect to see more from Cypress moving forward, and you will also certainly see us extend our portfolio.

Automotive MCUs Take on Performance /Power/Cost

Thursday, July 7th, 2016

Multicore architectures arrival on the scene poses new challenges for application designers.

The design challenge for automotive microcontrollers is to find a trade off between the ever-increasing demand for high processing speeds and low power consumption/low cost goals.

For a long time, silicon manufacturers increased processing speed and overall MCU performance with improvements in manufacturing and process technologies and with even more sophisticated core architectures, which meant increasing parallelism at the instruction level.

In this race to make processors faster, MCU designers have nearly exhausted the possibilities of alternative architectures, and MCU designs are becoming more complex and difficult to manage. And power consumption and heat dissipation are growing along with increases in MCU clock speed.

Designers are addressing the problem of balancing performance and power consumption by reducing clock speeds and redesigning the microcontroller’s architecture, putting multiple cores (two or more) on a die.

Yet the introduction of new MCU architectures creates fresh challenges for application designers, who have to take into account a new application development paradigms

Spurred by the fundamental need to boost performance, the evolution to multicore architectures requires distribution of the workload among the cores and applications by moving from a sequential to a parallel schema.

Shrinking Geometries and Growing Concerns
Automotive and other microcontrollers hunger for ever more computational power. The tradeoff between performance and power consumption (a key factor in the automotive sector) has been handled not only by increasing the operating frequency and implementing improvements at the core level (e.g. Instruction-level parallelism), but also by capitalizing on forward leaps in manufacturing technology and reducing the size of single gates.

For some time the only contribution to the challenge of using as little power as possible has been an approach related to the dynamic power that comes from the charge and discharge activity on the output of millions of gates. Because dynamic power is proportional to the square of supply voltage, reducing the voltage (and consequently the frequency) significantly lowers the power dissipated.

Unfortunately the “reduce-the-voltage” method is not iterative. Static power loss due to current leakage through transistor (subthreshold and oxide leakage) even when the transistors are turned off, considered negligible with geometries above 100nm, becomes a very prominent factor in the power budget when technology shrinks.

Nowadays the performance loss due to the slower operating frequency can be compensated by the use of multicore implementations that run the original tasks as parallel threads. Each thread executes in one core simultaneously to the others at slower operating frequency, so as to have total computational power unchanged compared to the serial case.

Several studies addressing the problem of delivering high performance while at the same time controlling leakage are in progress, and new technologies developed by the major silicon vendor players are under test to verify effectiveness. STMicroelectronics has introduced a promising innovation in silicon process called Fully Depleted Silicon On Insulator, or FD-SOI. This is a planar process technology that delivers the benefits of reduced silicon geometries while simplifying the manufacturing process.

Figure 1: One way to significantly cut down on leakage currents is with a buried oxide layer.

Figure 1: One way to significantly cut down on leakage currents is with a buried oxide layer.

The technology enables much better transistor electrostatic characteristics versus conventional bulk technology. The buried oxide layer (Figure 1) lowers the parasitic capacitance between the source and the drain while efficiently confining the electrons flowing from the source to the drain, dramatically reducing performance-degrading leakage currents.

Multicore Architectures
Multiple cores can run multiple instructions at the same time, increasing overall performance and allowing higher performance at lower energy. Each core in the multicore is generally more energy-efficient, so the chip becomes more efficient than were it to have a single large monolithic core. Assuming that the die can fit (physically) into the package, the multicore CPU designs require much less printed circuit board (PCB) space than multi-chip symmetric multiprocessing (SMP) designs.

A multicore processor uses slightly less power than more coupled single-core processors, principally because of the decreased power required to drive signals external to the chip. Maximizing the utilization of the computing resources provided by multicore processors requires adjustments or redesign to both to the operating system (OS) support and to the existing application software.

Some architectures use one core design repeated consistently (“homogeneous”), while others use a mixture of different cores, each optimized for a different, “heterogeneous” role. In other cases to meet the safety requirements two cores can exactly execute the same instruction (in lockstep mode) so as to compare output results. These kinds of dual-core couples (sometimes replicated on the same chip) are commonly used in Chassis and Safety designs, and in general in all applications targeting ASIL-D ISO26262 compliance. Sometimes on these devices it’s possible to completely separate (decouple) execution flow to ensure that software running on the primary core will not interrupt measurements and data processing on the secondary one.

Architecture Examples
STMicroelectronics has introduced the SPC56 Automotive MCU family, a versatile set of dual core devices that address such Automobile Body applications such as parking control and door control, as well as Chassis and Safety applications.

SPC56AP60 and SPC56ELx belong to Chassis and Safety family. They are both homogeneous multicore devices which embed the Power Architecture cores e200z0h (in the SPC56AP60) and e200z4d ( in the SPC56 ). In these MCUs the second core can be activated only by the primary core.

Figure 2: SPC56ELx Block Diagram

Figure 2: SPC56ELx Block Diagram

Figure 3: SPC56AP60 Block Diagram

Figure 3: SPC56AP60 Block Diagram

Specifically, SPC56ELx can work either in lockstep mode (both cores execute the same code in the same time from the power up) or in decoupled mode (execution flows are independent).

The Body family has instead a heterogeneous MCU (SPC56EC70) which applies as primary core an e200z4d and as secondary an e200z0h (Power Architecture). This device is focused on power saving during idle state. Therefore the second core exists mostly for low-power mode handling and doesn’t need to be as powerful as the main core.

Application Design
Designing a multicore application has its roots in the classical serial (for single core) design flow.

Figure 4: SPC56EC70 Block Diagram

Figure 4: SPC56EC70 Block Diagram

With the goal of boosting performance, designers, starting from serial optimization techniques, must move toward a parallel schema—where independent execution flows come together to solve large problems.

The two main factors that developers must take into account in parallel programming are a deep knowledge of the application and a clear understanding of the architecture where the application will run.

Understanding the application allows the developer to decompose where possible the serial execution flow into a parallel one. Deeper analysis of the application use case, including hotspots coming from profile information of serial implementations, can help in understanding the intrinsic nature of the problem that in general can be decomposed into task or data. While in task decomposition more tasks can be executed in parallel, since there are no dependencies. In data decomposition, large data manipulations can be split into smaller computational units.

Whatever the decomposition recognized or used, developers have to consider dependencies either for data manipulations or execution task ordering and finally choose a proper granularity that justifies the parallelization. Granularity, defined as the ratio of the number of computations to the number of communications, can be fine or coarse. With fine granularity, little portions of computation are done, and this usually implies a load balance across the architecture, which affects overall performance, since it can waste significant time in communication or synchronization with the other tasks. On the other hand a coarse-grained parallelism tends to increase the performance, but degrades the load balance.

In general more parallelism is desirable, but this doesn’t guarantee better performance. A successful performance balance relies on scheduling strategies, algorithm implementation, the most suitable granularity and the smart use of computational resources.

Application performance is strongly influenced by the structure of the code, and this is even more evident on multicore architectures, where the parallel executions incur overhead that limits the expected execution time benefits.

The user needs to find the correct tradeoff among having enough tasks to keep all cores busy, having enough computation in each task to amortize the overheads, and determining the optimal task size for achieving the shortest execution time.

Apart from the general development guidelines to reduce execution time and to save resources like compiler flags and low-level communications, the challenge in a multicore environment is to handle the overhead coming from inter-task interactions (e.g. synchronizations, data communications), hardware bookkeeping (e.g. memory consistency), software overheads (e.g. libraries), start-up and termination time for each function.

Good load balancing across a multicore platform is a must to obtain a good scaling of the application, and the scheduling strategy has to be carefully chosen.

In general a dynamic scheduling strategy usually introduces more overhead and is less scalable than static scheduling because it requires some global synchronization.

The weakness of the static scheduling arises when task duration is variable because it can generate an unbalanced load. In this case a very common solution is to split the tasks into a number of shorter tasks significantly larger than the number of the cores and apply to this a dynamic strategy to allocate the work on the idle cores while the parallel computation continues.

In general a fair load balance may conflict with data locality, and this of course may cause the waste of local memory resources available at core level.

In order to improve data alignment for better resource utilization and to reduce communication cost, it is reasonable to distribute data across the multicore architecture and keep it close to the core with primary use. Taking this approach means a strong use of local memories (TCM or system memories close to the core) and data tiling techniques over caches. However, apart from memory bandwidth weakness, a shared data model also implies that cache coherence must be ensured to allow multicore cache behavior to be consistent, as cores are seen as attached directly to the main memory. Improper or insufficient distribution of memory resources and the overhead of data synchronization may cause parallelized applications on multicore architectures to perform worse than serial use cases on a single-core device.

Moreover, in a multi-threading environment the competition for shared data or bus bandwidth can cause performance to deteriorate. Additional threads only waste on-chip power since performance execution drops.  A strong analysis is needed to choose the right number and the proper distribution of threads.

Conclusion
Successfully navigating the transition from single core devices to multicore architectures means users must change their design approach, either for application building or for computation methodology. A clear understanding of computational units and data flow content is needed to tackle application design and find a way ensure better performance with lower power consumption.

Raising performance comes with tradeoffs, and the applications will not increase performance or meet expectations unless the developer makes the effort to adapt the application to the device where it will run.

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Giovanni-D-AquinoGiovanni D’Aquino is senior application engineer for STMicroelectronics in Catania, Italy. He joined the company in 2003 and has been working in R&D as a software developer and OS expert. He has nine years experience in Power Architecture and currently works in the automotive microcontroller division as Chassis and Safety microcontroller’s application leader. D’Aquino graduated with a Master’s degree in Computer Engineering in 2002 and received his second Master’s specializing in Management of Development’s Projects about ICT Security in 2004.