Toshiba’s Fully Isolated N-channel LDMOS Realizes High HBM Robustness and High Breakdown Voltage to Negative Bias in 0.13-Micron Generation Analog Power Semiconductors



Toshiba has developed fully isolated N-channel LDMOS technology that overcomes the trade-off between breakdown voltage to negative bias (BVnb) and HBM robustness, a measure of resistance to electrostatic discharge (ESD).

Recent years have seen an increasing need for automotive analog ICs and Power ICs with fully isolated Nch-LDMOS and high BVnb, especially devices supporting voltages of 40V and over. Achieving a higher BVnb has until now required a trade-off with securing HBM robustness, and achieving both has required a bigger die, in order to electrically isolate substrates and the inside of the die. This has impeded progress in miniaturization and cost reduction. Furthermore, since HBM robustness is a parameter that is difficult to estimate without actually fabricating devices, a new parameter for estimating HBM robustness was strongly required.

In order to overcome the trade-off between HBM robustness and BVnb while minimizing die size, Toshiba conducted 2D TCAD simulations of numerous parameters and found that current flow concentration, which corresponds to the peak value of the electric field under the drain region (EUD), depends on HBM robustness. As a result of utilizing EUD to optimize die characteristics by adjusting various parameters, Toshiba successfully improved HBM robustness while achieving a rated voltage of 25 to 96V. This also realized a die size reduction of 46% for 80V fully isolated Nch-LDMOS products, satisfying HBM +/-4kV, a measure of HBM robustness.

Toshiba has produced prototypes of BiCD-0.13G3 process-based devices using the new technology and plans to start mass production in fiscal year 2018. The company is committed to contributing to the realization of lighter, more efficient automobiles and improving their performance by expanding the range of products offering fully isolated Nch-LDMOS.

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