Design Resources: USB 3.1 and Type-C

By: Chris A. Ciufo, Editor, Embedded Systems Engineering

An up-to-date quick reference list for engineers designing with Type-C.

USB 3.1 and its new Type-C connector are likely in your design near-future. USB 3.1 and the Type-C connector run at up to 10 Gbps, and Type-C is the USB-IF’s “does everything” connector that can be inserted either way (and never is upside down). The Type-C connector also delivers USB 3.1 speeds plus other gigabit protocols simultaneously, including DisplayPort, HDMI, Thunderbolt, PCI Express and more.

Also new or updated are the Battery Charging (BC) and Power Delivery (PD) specifications that provide up to 100W of charge capability in an effort to eliminate the need for a drawer full of incompatible wall warts.

If you’ve got USB 3.1 “SuperSpeed+” or the Type-C connector in your future, here’s a recent list of design resources, articles and websites that can help get you up to speed.

Start Here: The USB Interface Forum governs all of these specs, with lots of input from industry partners like Intel and Microsoft. USB 3.1 (it’s actually Gen 2), Type-C, and PD information is available via the USB-IF and it’s the best place to go for the actual details (note the hotlinks). Even if you don’t read them now, you know you’re going to need to read them eventually.

“Developer Days” The USB-IF presented this two-day seminar in Taipei last November 2015. I’ve recently discovered the treasure trove of preso’s located here (Figure 1). The “USB Type-C Specification Overview” is the most comprehensive I’ve seen lately.

Figure 1: USB-IF held a “Developer Days” forum in Taipei November 2015. These PPT’s are a great place to start your USB 3.1/Type-C education. (Image courtesy:

Figure 1: USB-IF held a “Developer Days” forum in Taipei November 2015. These PPT’s are a great place to start your USB 3.1/Type-C education. (Image courtesy:

What is Type-C? Another decent 1,000-foot view is my first article on Type-C: “Top 3 Essential Technologies for Ultra-mobile, Portable Embedded Systems.” Although the article covers other technologies, it compares Type-C against the other USB connectors and introduces designers to the USB-IF’s Battery Charging (BC) and Power Delivery (PD) specifications.

What is USB? To go further back to basics, “3 Things You Need to Know about USB Switches” starts at USB 1.1 and brings designers up to USB 3.0 SuperSpeed (5 Gbps). While the article is about switches, it also reminds readers that at USB 3.0 (and 3.1) speeds, signal integrity can’t be ignored.

USB Plus What Else? The article “USB Type-C is Coming…” overlays the aforementioned information with Type-C’s sideband capabilities that can transmit HDMI, DVI, Thunderbolt and more. Here, the emphasis is on pins, lines, and signal integrity considerations.

More Power, Scotty! Type-C’s 100W Power Delivery sources energy in either direction, depending upon the enumeration sequence between host and target. Components are needed to handle this logic, and the best source of info is from the IC and IP companies. A recent Q&A we did with IP provider Synopsys “Power Where It’s Needed…” goes behind the scenes a bit, while TI’s E2E Community has a running commentary on all things PD. The latter is a must-visit stop for embedded designers.

Finally, active cables are the future as Type-C interfaces to all manner of legacy interfaces (including USB 2.0/3.0). At last year’s IDF 2015, Cypress showed off dongles that converted between specs. Since then, the company has taken the lead in this emerging area and they’re the first place to go to learn about conversions and dongles (Figure 2).

Figure 2: In the Cypress booth at IDF 2015, the company and its partners showed off active cables and dongles. Here, Type-C (white) converts to Ethernet, HDMI, VGA, and one more I don’t recognize. (Photo by Chris A. Ciufo, 2015.)

Figure 2: In the Cypress booth at IDF 2015, the company and its partners showed off active cables and dongles. Here, Type-C (white) converts to Ethernet, HDMI, VGA, and one more I don’t recognize. (Photo by Chris A. Ciufo, 2015.)

Evolving Future: Although USB 3.1 and the Type-C connector are solid and not changing much, IC companies are introducing more highly integrated solutions for the BC, PD and USB 3.1 specifications plus sideband logic. For example, Intel’s Thunderbolt 3 uses Type-C and runs up to 40 Gbps, suggesting that Type-C has substantial headroom and more change is coming. My point: expect to keep your USB 3.1 and Type-C education up-to-date.

Intel Changes Course–And What a Change!

By Chris A. Ciufo, Editor, Embedded Intel Solutions

5 bullets explain Intel’s recent drastic course correction.

Intel CEO Brian Krzanich (Photo by author, IDF 2015.)

Intel CEO Brian Krzanich (Photo by author, IDF 2015.)

I recently opined on the amazing technology gifts Intel has given the embedded industry as the company approaches its 50th anniversary. Yet a few weeks later, the company released downward financials and announced layoffs, restructurings, executive changes and new strategies. Here are five key points from the recent news-storm of (mostly) negative coverage.

1. Layoffs.

Within days of the poor financial news, Intel CEO Brian Krzanich (“BK”) announced that 12,000 loyal employees would have to go. As the event unfolded over a few days, the pain was felt throughout Intel: from the Oregon facility where its IoT Intelligent Gateway strategy resides, to its design facilities in Israel and Ireland, to older fabs in places like New Mexico. Friends of mine at Intel have either been let go or are afraid for their jobs. This is the part about tech—and it’s not limited to Intel, mind you—that I hate the most. Sometimes it feels like a sweatshop where workers are treated poorly. (Check out the recent story concerning BiTMICRO Networks, which really did treat its workers poorly.)

2. Atom family: on its way out. 

This story broke late on the Friday night after the financial news—it was almost as if the company hadn’t planned on talking about it so quickly. But the bottom line is that the Atom never achieved all the goals Intel set out for it: lower price, lower power and a spot in handheld. Of course, much is written about Intel’s failure to wrest more than a token slice out of ARM’s hegemony in mobile. (BTW: that term “hegemony” used to be applied to Intel’s dominance in PCs. Sigh.) Details are still scant, but the current Atom Bay Trail architecture works very nicely, and I love my Atom-based Win8.1 Asus 2:1 with it. But the next Atom iteration (Apollo Lake) looks like the end of the line. Versions of Atom may live on under other names like Celeron and Pentium (though some of these may also be Haswell or Skylake versions).

3. New pillars announced.

Intel used to use the term “pillars” for its technology areas, and BK has gone to great lengths to list the new ones as: Data Center (aka: Xeon); Memory (aka: Flash SSDs and the Optane, 3D XPoint Intel/Micro joint venture); FPGAs (aka: Altera, eventually applied to Xeon co-accelerators); IoT (aka: what Intel used to call embedded); and 5G (a modem technology the company doesn’t really have yet). Mash-ups of these pillars include some of the use cases Intel is showing off today, such as wearables, medical, drones (apparently a personal favorite of BK), RealSense camera, and smart automobiles including self-driving cars. (Disclosure: I contracted to Intel in 2013 pertaining to the automotive market.)

 Intel’s new pillars, according to CEO Brian Krzanich. 5G modems are included in “Connectivity.” Not shown is “Moore’s Law,” which Intel must continue to push to be competitive.

Intel’s new pillars, according to CEO Brian Krzanich. 5G modems are included in “Connectivity.” Not shown is “Moore’s Law,” which Intel must continue to push to be competitive.

4. Tick-tock goodbye.

For many years, Intel has set the benchmark for process technology and made damn sure Moore’s Law was followed. The company’s cadence of new architecture (Tock) followed by process shrink (Tick) predictably streamed products that found their way into PCs, laptops, the data center (now “cloud” and soon “fog”). But as Intel approached 22nm, it got harder and harder to keep up the pace as CMOS channel dimensions approached Angstroms (inter-atomic distances). The company has now officially retired Tick-Tock in favor of a three-step process of Architecture, Process, and Process tuning. This is in fact where the company is today as the Core series evolved from 4th-gen (Haswell) to 5th-gen (Broadwell—a sort-of interim step) to the recent 6th-gen (Skylake). Skylake is officially a “Tock,” but if you work backwards, it’s kind of a fine-tuned process improvement with new features such as really good graphics, although AnandTech and others lauded Broadwell’s graphics. The next product—Kaby Lake (just “leaked” last week, go figure)—looks to be another process tweak. Now-public specs point to even better graphics, if the data can be believed.

Intel is arguably the industry’s largest software developer, and second only to Google when it comes to Android. (Photo by author, IDF 2015.)

Intel is arguably the industry’s largest software developer, and second only to Google when it comes to Android. (Photo by author, IDF 2015.)

5. Embedded, MCUs, and Value-Add.

This last bullet is my prediction of how Intel is going to climb back out of the rut. Over the years the company mimicked AMD and nearly singularly focused on selling x86 CPUs and variants (though it worked tirelessly on software like PCIe, WiDi, Android, USB Type-C and much more). It jettisoned value-add MCUs like the then-popular 80196 16-bitter with A/D and 8751EPROM-based MCU—conceding all of these products to companies like Renesas (Hitachi), Microchip (PIC series), and Freescale (ARM and Power-based MCUs, originally for automotive). Yet Intel can combine scads of its technology—including modems, WiFi (think: Centrino), PCIe, and USB)—into intelligent peripherals for IoT end nodes. Moreover, the company’s software arsenal even beats IBM (I’ll wager) and Intel can apply the x86 code base and tool set to dozens of new products. Or, they could just buy Microchip or Renesas or Cypress.

It pains me to see Intel layoff people, retrench, and appear to fumble around. I actually do think it is shot-gunning things just a bit right now, and officially giving up on developing low-power products for smartphones. Yet they’ll need low power for IoT nodes, too, and I don’t know that Quark and Curie are going to cut it. Still: I have faith. BK is hell-fire-brimstone motivated, and the company is anything but stupid. Time to pick a few paths and stay the course.

PCI Express Switch: the “Power Strip” of IC Design

Need more PCIe channels in your next board design? Add a PCIe switch for more fanout.

Editor’s notes:

1. Despite the fact that Pericom Semiconductor sponsors this particular blog post, your author learns that he actually knows very little about the complexities of PCIe.

2. Blog updated 3-27-14 to correct the link to Pericom P/N PI7C9X2G303EL.

Perhaps you’re like me; power cords everywhere. Anyone who has more than one mobile doodad—from smartphone to iPad to Kindle and beyond—is familiar with the ever-present power strip.

An actual power strip from under my desk. Scary...

An actual power strip from under my desk. Scary…

The power strip is a modern version of the age-old extension cord: it expands one wall socket into three, five or more.  Assuming there’s enough juice (AC amperage) to power it all, the power strip meets our growing hunger for more consumer devices (or rather: their chargers).


And so it is with IC design. PCI Express Gen 2 has become the most common interoperable, on-board way to add peripherals such as SATA ports, CODECs, GPUs, WiFi chipsets, USB hubs and even legacy peripherals like UARTs. The wall socket analogy applies here too: most new CPUs, SoCs, MCUs or system controllers lack sufficient PCI Express (PCIe) ports for all the peripheral devices designers need. Plus, as IC geometries shrink, system controllers also have lower drive capability per PCIe port and signals degrade rather quickly.

The solution to these host controller problems is a PCIe switch to increase fanout by adding two, three, or even eight additional PCIe ports with ample per-lane current sourcing capability.

Any Port in a Storm?

While our computers and laptops strangle everything in sight with USB cables, inside those same embedded boxes it’s PCIe as the routing mechanism of choice. Just about any standalone peripheral a system designer could want is available with a PCIe interface. Even esoteric peripherals—such as 4K complex FFT, range-finding, or OFDM algorithm IP blocks—usually come with a PCIe 2.0 interface.

Too bad then that modern device/host controllers are painfully short on PCIe ports. I did a little Googling and found that if you choose an Intel or AMD CPU, you’re in good shape. A 4th Gen Intel Core i7 with Intel 8 Series Chipset has six PCIe 2.0 ports spread across 12 lanes. Wow. Similarly, an AMD A10 APU has four PCIe (1x as x4, or 4x as x1). But these are desktop/laptop processors and they’re not so common in embedded.

AMD’s new G-Series SoC for embedded is an APU with a boatload of peripherals and it’s got only one PCIe Gen 2 port (x4). As for Intel’s new Bay Trail-based Atom processors running the latest red-hot laptop/tablet 2:1’s:  I couldn’t find an external PCIe port on the block diagram.

Similarly…Qualcomm Snapdragon 800? Nvidia Tegra 4 or even the new K1? Datasheets on these devices are closely held for customers only but I found Developer References that point to at best one PCIe port. ARM-based Freescale processors such as the i.MX6, popular in set-top boxes from Comcast and others have one lone PCIe 2.0 port (Figure 1).

What to do if a designer wants to add more PCIe-based stuff?

Figure 1: Freescale i.MX ARM-based CPU is loaded with peripheral I/O, yet has only one PCIe 2.0 port. (Courtesy: Freescale Semiconductor.)

Figure 1: Freescale i.MX ARM-based CPU is loaded with peripheral I/O, yet has only one PCIe 2.0 port. (Courtesy: Freescale Semiconductor.)

‘Mo Fanout

A PCIe switch solves the one-to-many dilemma. Add in a redriver at the Tx and Rx end, and signal integrity problems over long traces and connectors all but disappear. Switches from companies like Pericom come in many flavors, from simple lane switches that are essentially PCIe muxes, to packet switches with intelligent routing functions.

One simple example of a Pericom PCIe switch is the PI7C9X2G303EL. This PCIe 2.0 three port/three lane switch has one x1 Up and two x1 Down and would add two ports to the i.MX6 shown in Figure 1. This particular device, aimed at those low power consumer doodads I mentioned earlier, boasts some advanced power saving modes and consumes under 0.7W.

Hook Me Up

Upon researching this for Pericom, I was surprised to learn of all the nuances and variables to consider with PCIe switches. I won’t cover them here, other than mentioning some of the designer’s challenges: PCIe Gen 1 vs Gen 2, data packet routing, latency, CRC verification (for QoS), TLP layer inspection, auto re-send, and so on.

It seems that PCIe switches seem to come in all flavors, from the simplest “power strip”, to essentially an intelligent router-on-a-chip. And for maximum interoperability, of them need to be compliant to the PCI-SIG specs as verified by a plugfest.

So if you’re an embedded designer, the solution to your PCIe fanout problem is adding a PCI Express switch. 

The man asked: “Did Intel Lose Altera?”

Altera has made hay around Intel’s 14nm tri-gate (FinFET) process advantages. Have Intel’s Broadwell delays pushed Altera away?

In a recent post entitled “Did Intel Lose Altera?” blogger Ashraf Eassa muses at investment site The Motley Fool that Altera “is crawling back to Taiwan Semiconductor [TSMC]” for Altera’s high end Stratix 10 devices. His post is based upon an article originally written in DigiTimes which I’ve been unable to locate. (This article is similar, but speculates about Apple turning to Intel.)

Altera's Stratix 10 relies on multicore ARM Cortex A53s, DSP blocks, OpenCL, and Intel's 14nm Tri-Gate process.

Altera’s Stratix 10 relies on multicore ARM Cortex A53s, DSP blocks, OpenCL, and Intel’s 14nm Tri-Gate process.

The point, I assume, is Intel’s recent stumble with 14-nm Broadwell CPUs which were originally planned for Q4 2013, with production in Q1 2014 (now), but could possibly be postponed to Q4 2014 (says DigiTimes here).  3D transistors at this fine geometry are approaching rocket science so any delay even by the mighty Intel is not surprising and I’d consider pretty uneventful.

Except I’m not Intel–with a predictable Tick-Tock roadmap and that whole Moore’s Law thing–nor am I running Altera. The FPGA company Altera, of course, is trying to one-up Xilinx who so far is sticking with TSMC’s 20nm goodness.

  • I offer some good insight into Altera’s Stratix 10 plans for Intel’s foundry here.
  • For some insight on Xilinx’s UltraScale products in TSMC’s process, read here.

All of this is playing out under the microscope of Intel’s shallow penetration into the mobile (smartphone and tablet) markets where ARM-based SoCs from Nvidia, Qualcomm and others seem to obviate the dramatic advances Intel has made with their Bay Trail and Quark roadmaps.  So Intel can’t afford any bad press to the financial community.

I’m a fan of Intel, believe they’ll dominate again, and give them kudos for countless new-generation Atom design wins in Windows 8.1, Android, Tizen and other mobile devices. And I’m stoked about how Intel is evolving the all-day battery UltraBook into the 2:1 laptop/tablet. Still, ARM’s licensees dominate this landscape.

So we’ll keep an eye on this story since it intersects several others we’ve posted in the past few months.


Some insight into Altera’s Stratix 10 plans

Hint: Intel’s 14nm tri-gate (FinFET) process is at the core (no pun) of Altera’s recipe, but architecture and software tools round out new FPGA family plans.

Figure 5 Altera SoC roadmap (PNG)First to announce plans for a quad-core ARM Cortex A53-based SoC FPGA, Altera will rely on their Intel fab exclusivity to provide what an Altera spokesman called “unimaginable performance”. One of the titans in the FPGA market (the other is Xilinx), Altera has been slowly opening the curtain on their roadmap plans.

I’ve been following and reporting on Altera’s announcements, acquisitions, and possible strategies for the last 12 months. Now, all is revealed in the company’s Stratix 10 technology announcement. An in-depth report (with links) is available here.

Editor’s note: While Altera is announcing their technology plans, Xilinx announced new 20nm devices in Virtex and Kintex UltraScale devices. Our in-depth report on Xilinx will follow shortly.  C. Ciufo, editor.

Lattice Brings Reuse from Smartphones to General Embedded

Three new Lattice FPGA reference designs show how smartphone components such as cameras or SoCs with MIPI interfaces can be “bridged” into general embedded applications like automotive.

Lattice today announced three complete reference designs–based upon their FPGAs, of course–that show how users can reuse/repurpose smartphone designs in non-smartphone applications.  If the component, such as the SoC application processor, camera sensor, or even RF front-end, uses the industry-standard MIPI interface (Mobile Industry Processor Interface), Lattice has a way to bridge that device to other components.

Lattice FPGAs in three new reference designs bridge smartphone any embedded design.

Lattice FPGAs in three new reference designs bridge smartphone MIPI…to any embedded design.

Automobiles, for instance, now incorporate forward-looking cameras for lane departure, and driver-facing cameras to gauge alertness. Neither of these applications are smartphones but with Lattice’s help could utilize low-power smartphone CMOS image sensors.

Subaru's EyeSight system uses twin forward-facing cameras for lane departure and other adaptive safety features. (Courtesy: Subaru of America.)

Subaru’s EyeSight system uses twin forward-facing cameras for lane departure and other adaptive safety features. (Courtesy: Subaru of America.)

It’s an interesting concept that’s not only useful, but brings Lattice back into focus as a niche supplier of specialty FPGAs that aren’t behemoth power processors like those from Altera or Xilinx.  I say hat’s off to Lattice. We’ll watch this evolve and keep you updated.



Does Altera Have “Big Data” Communications on the Brain?

In wireless, wireline and financial “big data” applications, moving all those packets needs prodigious FPGA resources, not all of which Altera had before their recent series of acquisitions, partnerships, and otherwise wheeling-and-dealing.

Chris Balough of Altera (left) interviewed by Andy Frame from ARM. (Courtesy: YouTube.)

Chris Balough of Altera (left) interviewed by Andy Frame from ARM. (Courtesy: YouTube.)

I caught up with an old friend at April’s DESIGN West 2013 conference in San Jose: Chris Balough, Sr Director, Product Marketing for SoC products. I knew Chris from when he was at Triscend (purchased by Xilinx). Chris is now in charge of Altera’s SoC products which are Arria V, Stratix V and Cyclone FPGAs with ARM cores in them which compete with Xilinx’s Zynq devices. Chris shed some light on some of these announcements, but remained mum on what they all might mean taken collectively. I think they add up to something big in “Big Data”.

(Fun facts: Altera’s first “SoC” was Excalibur, no longer recommended for new designs. Altera’s most popular SoC processor is the soft Nios II, sold in roughly 30 percent of production SoCs, says Balough.)

X before A? We’ll See

Subconsciously I think of Xilinx first when the word “FPGA” is flashed in front of me, but Altera’s the company pushing more boundaries of late. Their rat-a-tat machine gun announcements this year got my attention.

In the summer of 2012, I did an interview with Altera’s Sr VP of R&D Brad Howe and he spread out as much of the roadmap on the table as he could. Things like HSA, OpenCL, and better gigabit transceivers were all on the horizon.  Shortly thereafter, Altera extended their  relationship with TSMC to 20nm for Arria and Cyclone FPGAs. Then in early 2013, they rocked the industry by locking up an exclusive FPGA relationship with Intel for the industry’s only production 14nm tri-gate FinFETs.

Spring Cleaning ; Altera’s Getting Ready For…?

Now in Spring 2013, Altera is making headlines like these:

- FPGA Design in the Cloud–Try It, You’ll Like It, Says Plunify. At DAC, Altera and Plunify are pushing cloud-based FPGA design tools. (See our February 2013 article with Plunify here.)

- Altera and AppliedMicro will Cooperate on Joint Solutions for High Growth Data Center Market.  Combines Stratix FPGAs and AppliedMicro’s Server on a Chip devices targeting data centers and optical transport networks (OTN).

- Altera Expands OTN Solution Capabilities with Acquisition of TPACK. Altera buys TPAK from AMCC to provide IP for FPGAs used in OTN for tasks like cross-bar switches used in 10/40/100Gbps PHYs.

- Altera Stratix V GX FPGAs Achieve PCIe Gen3 Compliance and Listing on PCI-SIG Integrators List. Right now, Gen2 and Gen3 PCIe is critical to data centers, cellular base stations, and all manner of high-speed long-haul/back-haul telco gear. Within 12 months, PCIe Gen2/3 will be “table stakes” in all manner of high-performance embedded systems like ATCA- or VME/VPX-based DSP systems for radar, sonar, SIGINT (signals intelligence) or data mining.

- Altera to Deliver Breakthrough Power Solutions for FPGAs with Acquisition of Power Technology Innovator Enpirion.  Maybe Enpirion’s DC-DC converter PowerSoCs with integrated inductors may some day end up inside a Stratix package (perhaps like Xilinx’s stacked chip interposer technology), but for now the two-chip solution reduces board space by 1/7 and simplifies system design considerably. The programmable DC-DC converters provide the multiple power rails–and power-up sequences–needed for big FPGAs.

The blue regions show places where FPGAs are used in wireless basestations.

The blue regions show places where FPGAs are used in wireless LTE basestations. (Courtesy: Altera.)

My Take: Altera’s Move in Big Data

Analysts estimate that nearly 50 percent of the revenue in  FPGAs comes from high end, high density, costly FPGAs like the Xilinx Vertex 7 and Altera Stratix V. Segments like wireless and wireline packet processing, plus financial or image processing algorithm processors increasingly rely on these kinds of FPGAs in lieu of ASICs, GPGPUs, or proprietary network processors. So every advantage in IP, process technology, or partnership that Altera has, gets the company one step closer to more design wins.

We’ll see what Altera does with all of these recent announcements. I’d expect to see something shake loose before the traditional “summer doldrums” set in when the semiconductor industry goes on its annual vacation next month in July.