Chip Design Resource Center

From the Blogosphere

  • The return of the CEO Outlook

    The ESD Alliance is relaunching the annual panel session featuring CEOs from ARM, Cadence Design Systems, Mentor Graphics and Synopsys in Mountain View on April 9....

  • Blog Post: Know your gate driver

    I hope you’ve had a chance to watch our video series, “ Know Your Gate Driver .” Although often overlooked, gate drivers are responsible for a lot of the heavy lifting in systems like power supplies and motor-control systems. I like to think of a gate driver as a muscle ! The video series explains how while highlighting...

  • AMS SIG India, 2017 – Update

    Happy Wednesday folks! If you recall, AMS SIG India was held in Bengaluru last month (2/16/17). It was well attended and quite successful! Distinguished speakers from Samsung, Xilinx, Qualcomm, STMicroelectronics, and Synopsys R&D, spoke on a wide variety of topics centered around the use of Synopsys solutions to address...

  • Specman in Xcelium

    Just recently Cadence announced the new superb simulator, Xcelium . Just as Specman was part of the previous simulator, IES, it is now part of Xcelium. As always, we keep enhancing and developing Specman, and the new Specman release, now part of Xcelium, contains great new capabilities. The focus in the last year was on...

Featured Articles

  • Technology Convergence Enables Industrial IoT Solutions

    Ever since Thomas Edison flipped the switch to power the first electric light, the pace of electronic innovation has never let up. With the invention of the transistor and then the

  • Long Haul Harmony Q&A with Mahbubul Alam, Movimento

    Editor’s note:  Yes, some of us love our cars, but however passionate we are about them they don’t figure as largely in our lives as a truck does for a professional long-haul truck

  • Intel’s 10nm Enigma

    I’ve been looking back at the talk given by Mark Bohr and Zane Ball (Building Winning Products with Intel® Advanced Technologies and Custom Foundry Platforms) at the Intel Developer

  • How Ethernet Will Get to 400Gbps

    The IEEE 802.3bs standard for 400Gbps is on track to be ratified and released late this year. Part of the secret is PAM4, a clever encoding method that instantly doubles throughput. Ethernet

  • How Modular Fog Servers Advance Industry 4.0

    The future of Industry 4.0 systems across all sectors lies in the combination of fog server and real-time technology. Robots, machines and manufacturing systems that are integrated

  • Why is Chip Design for IOT so Hard?

    Internet-of-Things (IOT) designers face a different set of challenges from their traditional ASIC and SOC brethren. Will the market be ready?

  • Smart Thinking

    Smart meters are well-established, but companies are still finding ways to improve communications and smart energy management. The two-way communications and data systems of smart

  • The New Driver for Semiconductor Tech

    By Pete Singer, Editor-in-Chief Over the past 40 years, the electronics industry has gone through three distinct stage or “waves” of evolution. Last year, in a Solid State Technology

Featured Products

  • Mixel’s MIPI D-PHY RX+

    Organizations: GSA, MIPI Alliance D-PHY RX+ is a CSI and DSI D-PHY Receiver optimized for small area and low power, while achieving full-speed production testing, in-system testing,

  • Mixel’s MIPI C-PHY/D-PHY Combo

    Organizations: GSA, MIPI Alliance Mixel’s MIPI C-PHY/D-PHY Combo is a high-frequency low-power, low-cost, source-synchronous, physical layer. The PHY can be configured as a MIPI

  • Timing Constraints - Done Once! Done Right!

    Organizations: EDAC, GSA, Si2 Constraints-Manager (ConMan), Constraints-Certifier (ConCert), Exceptions Toolbox and Clock Domain Crossing Review (ConDor) End to End timing constraints

  • SOS Design Data & IP Management Platform

    ClioSoft ClioSoft’s SOS Design Collaboration Platform is built to handle the complex requirements of system-on-chip design flows. The SOS platform provides a sophisticated multi-site

  • Industry Leading Tools Linking Simulation and ATPG to Test

    Source III provides the industry’s most comprehensive and cost-effective vector translation product (VTRAN®) which links simulation/ATPG vector data to ATE, a powerful vector analysis

  • Mixel’s MIPI M-PHY

    Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI® Alliance Specification for M-PHY®. The

  • IDesignSpec™

    IDesignSpec™ is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically generate

  • IDesignSpec™

    IDesignSpec™is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically generate

Chip Design Datasheet Directory

    EDA Tools

    Verification Functional

  • by AMIQ EDA

    Design and Verification Tools (DVT) is an integrated development environment (IDE) for the e language, SystemVerilog, Verilog, and VHDL. It helps design and verification engineers...

  • by AMIQ EDA

    Thorough audit of your test benches Verissimo SystemVerilog Testbench Linter is a static code analysis tool that allows engineers to perform a thorough audit of their testbenches....

  • Methods / EDA Tools

  • by ClioSoft Inc.

    ClioSoft ClioSoft’s SOS Design Collaboration Platform is built to handle the complex requirements of system-on-chip design flows. The SOS platform provides a sophisticated multi-site...

  • Design-for-Test (DFT)

  • by Source III, Inc.

    Source III provides the industry’s most comprehensive and cost-effective vector translation product (VTRAN®) which links simulation/ATPG vector data to ATE, a powerful vector...

  • by Source III, Inc.

    With nearly 25 years of field-proven success, VTRAN™ offers the most cost-effective, full-feature solution to creating EDA and ATE test programs from simulation and ATPG vectors....

  • Verification

  • by Agnisys

    IDesignSpec™is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically...

  • by Agnisys

    IDesignSpec™ is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically...

  • by Excellicon

    Organizations: EDAC, GSA, Si2 Constraints-Manager (ConMan), Constraints-Certifier (ConCert), Exceptions Toolbox and Clock Domain Crossing Review (ConDor) End to End timing...

  • by Real Intent

    Meridian CDC is the fastest, highest capacity and most precise clock domain crossing (CDC) solution in the market. It performs comprehensive structural and functional analysis...

  • by Sutherland HDL, Inc

    Founded in 1992, Sutherland HDL has trained thousands of engineers throughout the world on Verilog, SystemVerilog, SVA and UVM. WORKSHOP HIGHLIGHTS Verilog and SystemVerilog...

  • Semiconductor Technologies

    IP - Core

  • by Calypto Design Systems

    Accelerate Time to Rtl, Reduce Verification Effort
    The Catapult® high-level synthesis tool empowers designers to use industry standard ANSI C++ and SystemC to describe functional intent, and move up to a more productive abstraction level.

  • by Calypto Design Systems

    With the explosion of consumer electronics, designing for low-power has become an important design constraint and a key differentiating factor. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, both via automated tools as well as manually by the RTL designers.

  • by Calypto Design Systems

    The emergence of consumer electronics is causing a fundamental shift in Register Transfer Level (RTL) design methodologies. The race for time to market has resulted in the adoption and growth of higher level design creation methodologies. In particular, High Level Synthesis (HLS) directly from software models to hardware has become very popular.

  • by Mixel, Inc.

    Organizations: GSA, MIPI Alliance Mixel’s MIPI C-PHY/D-PHY Combo is a high-frequency low-power, low-cost, source-synchronous, physical layer. The PHY can be configured as...

  • by Mixel, Inc.

    Organizations: GSA, MIPI Alliance D-PHY RX+ is a CSI and DSI D-PHY Receiver optimized for small area and low power, while achieving full-speed production testing, in-system...

  • by Mixel, Inc.

    Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI® Alliance Specification for M-PHY®....

  • by SmartDV Technologies India Private Limited

    Organizations: EDAC, GSA, EIC, OCP-IP, Si2, SPIRIT SmartDV offers wide range of Verification IP’s, Memory models and Design IP’s. Verification models include complete...

  • by True Circuits Inc.

    Organizations: GSA The TCI DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually,...

  • by True Circuits Inc.

    Organizations: GSA True Circuits’ complete family of standardized, silicon-proven, low-jitter PLL and DLL hard macros spans nearly all performance points and features typically...