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Collaboration Also Enables In-Design Physical Verification with IC Compiler MOUNTAIN VIEW, Calif. and HSINCHU, Taiwan, April 23, 2014 /PRNewswire/ -- Highlights: UMC extends
From the Blogosphere
Altera has revealed that the DSP blocks in the Arria 10 FPGAs contain the logic needed to make them work as IEEE754-compliant floating-point units....
Hello,Other people try to access my xampp web through my ip address in my private network but unable to do so. How to make it work?I already try to reinstall my xampp yet it still does not work. Is there any specific way to make it work?Thanks before....
Last week at VLSI Test Symposium (VTS) 2014, Synopsys presented “Fault Modeling and Test Algorithm Creation Strategy for FinFET-Based Memories” to a packed room of attendees with several standing, all interested in learning about memory Test for FinFET. FinFET transistors are playing an important role in advanced process...
Cadence has lagged behind in formal verification tools, which it plans to remedy by acquiring the JasperGold Apps suite. Cadence will integrate Jasper's formal analysis toolkit into the Cadence System Development Suite to create the most comprehensive set of verification tools available today, according to the companies:...
Initiated by Apple’s launch of the iPhone, the subsequent explosive growth of the smartphone market has provided the MEMS industry with one of its biggest opportunities to supply
Should foundries establish and share best practices to manage sub-nanometer effects to improve yield and also manufacturability? Team effort Design for yield (DFY) has been referred
Today's always-on, cloud-connected electronic products create value by delivering massive amounts of data on time to serve a wide variety of applications. Whether streaming video, transacting
Projected growth in the third-party semiconductor intellectual-property (IP) market through 2017 may affect the direction and evolution of subsystem designs.
Earlier warnings by Berkeley's Dr. Rabaey are echoed in ARM-Economist report.
While 6 billion people know about USB on the outside of smartphones, cameras, and laptops, only product designers are familiar with how USB is used inside of these products. In laptops, for example, the touchpad, webcam, and broadband modem often use standard USB parts—consuming standard USB power—internally.
I recently had lunch with a dejected engineer from a semiconductor startup in big trouble. After months of effort at no small expense, the chip design project was an utter failure,
Power impact is greatest above the gate level
In Part II, IP Extreme’s Savage reveals why IP standards take so long while discussing brand values, macro trends, and changes wrought by patent trolls.
Definitions vary but implications for the Internet of Things does not.
Meridian CDC is the fastest, highest capacity and most precise clock domain crossing (CDC) solution in the market. It performs comprehensive structural and functional analysis to ensure
Design and Verification Tools (DVT) is an integrated development environment (IDE) for the e language, SystemVerilog, Verilog, and VHDL. It helps design and verification engineers
Organizations: GSA The TCI DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually,
Organizations: EDAC, GSA, EIC, OCP-IP, Si2, SPIRIT SmartDV offers wide range of Verification IP’s, Memory models and Design IP’s. Verification models include complete MIPI protocol
Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI® Alliance Specfication for M-PHY®. The IP
Organizations: GSA True Circuits’ complete family of standardized, silicon-proven, low-jitter PLL and DLL hard macros spans nearly all performance points and features typically
With the explosion of consumer electronics, designing for low-power has become an important design constraint and a key differentiating factor. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, both via automated tools as well as manually by the RTL designers.