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At the ARM TechCon, Pete Hutton, president of ARM’s products group touched on many new developments and announcements, including HP’s 64-bit ARM-based server, big.LITTLE MP, OpenCL, JUNO, DuoLog/Socrates, Artisan/PowerGrid Architect, and Cortex M7.
From the Blogosphere
Cadence Design Systems has built a verification environment around its vManager software for ICs and systems that need to conform to the ISO 26262 safety standard....
Brooke Williams doesn’t have to look far to find inspiration for his work on the TDA3x automotive system on a chip (SoC) family used in advanced driver assistance systems (ADAS). The business manager for ADAS just glances at the picture frames on his desk. “I have three kids who are not yet driving, but one...
Hi there, I am working on signature based IDS, for this I have captured the TCP/IP traffic through Wireshark and got a pcap file, I want to extract some fields from the packet itself. How do I do this? I have been searching through the Internet and got the idea ......
For years we've watched the e and SystemVerilog race via countless presentations, articles, and blogs. Each language is applied to SoC verification yet the differences are well documented so any comparison is subject to recoding from one language to the other. This makes a direct performance comparison difficult to...
The health benefits in our future might just rest on how hale, hardy (and cost-effective) developers, including start-ups, can make their implantable medical device proof-of-concepts—and that warrants a close look at ASSP chips for help with size, power and development time hurdles.
Embedded designers can follow a roadmap to alleviate graphics challenges when developing for mobile medical, smartphones/tablets, gaming, HDTV and more. With today’s mobile devices
Sensor networks for consumer and industrial applications can benefit from low-power RF technologies combined with hardware encryption for safeguarding data.
These days, you’d need to be buried under a pile of verification reports not to know that hardware emulation has gone mainstream, moving away from a dusty back room to your cubemate’s
We all know that it’s only a matter of time until our cars are able to communicate with each other. Another wave of connectivity-focused innovation is underway and, this time around,
With anticipated economic limits to the continuation of Moore’s Law now on the horizon, it seems that moving into the 3rd dimension (3D) by stacking multiple layers of integrated
Introduction IEEE 1149.1-2013 is not your father's JTAG. The new release in June of 2013 represents a major leap forward in standardizing how FPGAs, SoCs and 3D-SICs can be debugged
Traditional black box methodologies give way to a novel grey-cell approach for intellectual property (IP) and FPGA clock domain crossing (CDC) analysis. As design complexity escalates,
An on-chip network offers a set of services that allow chip designers and architects to optimize the design to meet the real world requirements of today’s devices, including those
There are many challenges when designing ICs that contain tens to hundreds of millions of gates and it won't get any easier as next-generation designs cross the gigagate threshold.
Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI® Alliance Specification for M-PHY®. The
IDesignSpec™ is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically generate
Founded in 1992, Sutherland HDL has trained thousands of engineers throughout the world on Verilog, SystemVerilog, SVA and UVM. WORKSHOP HIGHLIGHTS Verilog and SystemVerilog
With nearly 25 years of field-proven success, VTRAN™ offers the most cost-effective, full-feature solution to creating EDA and ATE test programs from simulation and ATPG vectors.
IDesignSpec™is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically generate
Meridian CDC is the fastest, highest capacity and most precise clock domain crossing (CDC) solution in the market. It performs comprehensive structural and functional analysis to ensure
Organizations: GSA The TCI DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually,