Chip Design Resource Center
Top Stories and News
| New White Papers |
Increased Investment Supports Growing Customer Base in Europe ProPlus Design Solutions, Inc., the SPICE modeling solutions leader and provider of the first giga-scale SPICE simulator
From the Blogosphere
Cisco has decided to buy memory-controller specialist Memoir Systems and absorb the technology into its Insieme business unit, which specializes in data-center switch technologies, a move that underlines the issues facing small IP suppliers and their customers....
Yar Mateys! I’ve been told today is “Pirate Appreciation Day,” or as you land lubbers call it, “Talk Like a Pirate Day.” A day where all those who sail the seven seas stop and raise a mug of grog and appreciate all the hard work thar be into being a pirate. What’s that you...
My ws0 is trying to ping 10.xx.2.1 and doesnt have an arp cache. I understand what the first redirect is for since my BR is sending the ws0 to look for that ip at R3, what is the second redirect for?...
Verification engineers spend lots of time creating tests. In fact, creating enough tests to verify the design functionality consistently tops the list of verification challenges, according to periodic surveys of our customers. One challenge in test creation is that verification occurs in multiple environments. For high-level...
Sensor networks for consumer and industrial applications can benefit from low-power RF technologies combined with hardware encryption for safeguarding data.
These days, you’d need to be buried under a pile of verification reports not to know that hardware emulation has gone mainstream, moving away from a dusty back room to your cubemate’s
We all know that it’s only a matter of time until our cars are able to communicate with each other. Another wave of connectivity-focused innovation is underway and, this time around,
With anticipated economic limits to the continuation of Moore’s Law now on the horizon, it seems that moving into the 3rd dimension (3D) by stacking multiple layers of integrated
Introduction IEEE 1149.1-2013 is not your father's JTAG. The new release in June of 2013 represents a major leap forward in standardizing how FPGAs, SoCs and 3D-SICs can be debugged
Traditional black box methodologies give way to a novel grey-cell approach for intellectual property (IP) and FPGA clock domain crossing (CDC) analysis. As design complexity escalates,
An on-chip network offers a set of services that allow chip designers and architects to optimize the design to meet the real world requirements of today’s devices, including those
There are many challenges when designing ICs that contain tens to hundreds of millions of gates and it won't get any easier as next-generation designs cross the gigagate threshold.
Initiated by Apple’s launch of the iPhone, the subsequent explosive growth of the smartphone market has provided the MEMS industry with one of its biggest opportunities to supply
Should foundries establish and share best practices to manage sub-nanometer effects to improve yield and also manufacturability? Team effort Design for yield (DFY) has been referred
Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI® Alliance Specification for M-PHY®. The
IDesignSpec™ is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically generate
Founded in 1992, Sutherland HDL has trained thousands of engineers throughout the world on Verilog, SystemVerilog, SVA and UVM. WORKSHOP HIGHLIGHTS Verilog and SystemVerilog
With nearly 25 years of field-proven success, VTRAN™ offers the most cost-effective, full-feature solution to creating EDA and ATE test programs from simulation and ATPG vectors.
IDesignSpec™is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically generate
Meridian CDC is the fastest, highest capacity and most precise clock domain crossing (CDC) solution in the market. It performs comprehensive structural and functional analysis to ensure
Organizations: GSA The TCI DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually,