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World’s first semiconductor IP to support both HEVC and VP9 video formats VeriSilicon Holdings Co., Ltd. (VeriSilicon), a leading custom silicon solutions and semiconductor
From the Blogosphere
When you beef-up an ARM processor to run a high-end operating system, such as Windows 8, it looses its low-cost/low-power advantage over Intel application processors, according to ABI Research: R. Colin Johnson @NextGenLog Further Reading...
Design security is a major target for Microsemi’s update to its Igloo series of flash memory-based FPGAs, which add an ARM-oriented memory subsystem.The post Microsemi focuses on security with Igloo2 FPGAs appeared first on Tech Design Forum....
Blog Post: Innovation through smart integration – achieving lower power, high performing small cells
Wireless small cell market activity is accelerating lately and last week’s Small Cell World Summit in London, with its 50% increase in attendance, certainly reflected some of the industry excitement. Small cell enterprise solutions and associated powering and backhaul challenges, as well as integrated Wi-FI functionality...
I've written a lot about the benefits of moving hardware design and verification up in abstraction from RTL to SystemC with transaction-level models (TLM). We have seen many customers speed their overall design and verification turnaround by 2x. A recent article described Fujitsu Semiconductor's experience -- 35%...
AWR Corporation, the innovation leader in high-frequency EDA software, is proud to announce that Sherry Hess, vice president of marketing and long time advocate for women in engineering,
What are the new technologies in the arena?
PCIe is following USB into mobile chip-to-chip applications by adopting the low-power MIPI M-PHY.
IP giant also talks about Intel, finFETs and the cloud Needless to say, ARM Holdings is the dominate supplier of processor intellectual property (IP) in the booming cell-phone
Designing a glucose monitoring device is made easy with an 8-bit, 8051-based Programmable SoC
Cloud computing will play an increasingly significant role in FPGA designs because the benefits to designers are tremendous. Chip design engineers face a myriad of challenges in
Lattice and Xilinx muse on parallelism, partial reconfigurability, and the state-of-the-art in IP and EDA tools.
Tackling the Challenge of Building Smaller, Lighter, and More Efficient Component-based Avionics with CFD
Computational Fluid Dynamics software helps defense systems designers doubly: it aids in optimizing component SWaP, and models device thermal behavior across time and vendors.
A subtle but important shift is under way inside of EDA. While vendors are still focused on solving some thorny issues at the front end of Moore’s Law, much of the R&D effort
Will the success of the open source movement in software and even hardware cause changes in silicon IP business models?
Organizations: GSA True Circuits’ complete family of standardized, silicon-proven, low-jitter PLL and DLL hard macros spans nearly all performance points and features typically
With the explosion of consumer electronics, designing for low-power has become an important design constraint and a key differentiating factor. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, both via automated tools as well as manually by the RTL designers.
The emergence of consumer electronics is causing a fundamental shift in Register Transfer Level (RTL) design methodologies. The race for time to market has resulted in the adoption and growth of higher level design creation methodologies. In particular, High Level Synthesis (HLS) directly from software models to hardware has become very popular.
Accelerate Time to Rtl, Reduce Verification Effort
The Catapult® high-level synthesis tool empowers designers to use industry standard ANSI C++ and SystemC to describe functional intent, and move up to a more productive abstraction level.