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A new low power I/Q modulator from Linear Technology enables battery-powered transmitters operating in the 30MHz to 1.3GHz frequency bands, breaking new ground in power consumption,
From the Blogosphere
Blog Post: DIY with TI: TIer wakes up to robotic, moving alarm clock (with a cymbal-holding monkey on top!)
Like many college kids, Zahid Haq overslept a few times when he was a student at the University of Texas at Austin (UT). What Zahid needed was a reliable, noisy alarm clock that could really get his attention. Now working as a Bluetooth applications engineer at TI, the 24-year-old still has a little trouble getting up...
The ever popular Accellera Design & Verification Conference held annually in Silicon Valley is going global. Accellera System Initiative has expanded many of its SystemC user group events to be more inclusive of other Accellera and IEEE standards. In doing so, the local organizers of these events have moved to adopt...
With all the requests by scientists and the government for money lately, here, finally, is something you can get from the government… for free. Yes, that’s right, applicable scientific and engineering tools that are the result of NSF funding that your taxes paid for and that you can actually use… today…...
System-on-Chip (SoC) building can now be learned by any academic, giving them access to EDA tools and the training they need t use them from a special cloud server: R. Colin Johnson @NextGenLogCloud-based virtual machines provide the EDA tools, design databases, intellectual property, workflows, and more to universities...
Sensor networks for consumer and industrial applications can benefit from low-power RF technologies combined with hardware encryption for safeguarding data.
These days, you’d need to be buried under a pile of verification reports not to know that hardware emulation has gone mainstream, moving away from a dusty back room to your cubemate’s
We all know that it’s only a matter of time until our cars are able to communicate with each other. Another wave of connectivity-focused innovation is underway and, this time around,
With anticipated economic limits to the continuation of Moore’s Law now on the horizon, it seems that moving into the 3rd dimension (3D) by stacking multiple layers of integrated
Introduction IEEE 1149.1-2013 is not your father's JTAG. The new release in June of 2013 represents a major leap forward in standardizing how FPGAs, SoCs and 3D-SICs can be debugged
Traditional black box methodologies give way to a novel grey-cell approach for intellectual property (IP) and FPGA clock domain crossing (CDC) analysis. As design complexity escalates,
An on-chip network offers a set of services that allow chip designers and architects to optimize the design to meet the real world requirements of today’s devices, including those
There are many challenges when designing ICs that contain tens to hundreds of millions of gates and it won't get any easier as next-generation designs cross the gigagate threshold.
Initiated by Apple’s launch of the iPhone, the subsequent explosive growth of the smartphone market has provided the MEMS industry with one of its biggest opportunities to supply
Should foundries establish and share best practices to manage sub-nanometer effects to improve yield and also manufacturability? Team effort Design for yield (DFY) has been referred
Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI® Alliance Specification for M-PHY®. The
IDesignSpec™ is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically generate
Founded in 1992, Sutherland HDL has trained thousands of engineers throughout the world on Verilog, SystemVerilog, SVA and UVM. WORKSHOP HIGHLIGHTS Verilog and SystemVerilog
With nearly 25 years of field-proven success, VTRAN™ offers the most cost-effective, full-feature solution to creating EDA and ATE test programs from simulation and ATPG vectors.
IDesignSpec™is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically generate
Meridian CDC is the fastest, highest capacity and most precise clock domain crossing (CDC) solution in the market. It performs comprehensive structural and functional analysis to ensure
Organizations: GSA The TCI DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually,