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From the Blogosphere

  • Altera finds a way to cheaper floating point in FPGAs

    Altera has revealed that the DSP blocks in the Arria 10 FPGAs contain the logic needed to make them work as IEEE754-compliant floating-point units....

  • Akses xampp through private network

    Hello,Other people try to access my xampp web through my ip address in my private network but unable to do so. How to make it work?I already try to reinstall my xampp yet it still does not work. Is there any specific way to make it work?Thanks before....

  • Sharpen your FinFET memory test

    Last week at VLSI Test Symposium (VTS) 2014, Synopsys presented “Fault Modeling and Test Algorithm Creation Strategy for FinFET-Based Memories” to a packed room of attendees with several standing, all interested in learning about memory Test for FinFET. FinFET transistors are playing an important role in advanced process...

  • #EDA: Cadence Design Systems Acquires Jasper Design Automation"

    Cadence has lagged behind in formal verification tools, which it plans to remedy by acquiring the JasperGold Apps suite. Cadence will integrate Jasper's formal analysis toolkit into the Cadence System Development Suite to create the most comprehensive set of verification tools available today, according to the companies:...

Featured Articles

Featured Products

  • Meridian CDC

    Meridian CDC is the fastest, highest capacity and most precise clock domain crossing (CDC) solution in the market. It performs comprehensive structural and functional analysis to ensure

  • Design and Verification Tools (DVT)

    Design and Verification Tools (DVT) is an integrated development environment (IDE) for the e language, SystemVerilog, Verilog, and VHDL. It helps design and verification engineers

  • DDR 4/3 PHY

    Organizations: GSA The TCI DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually,

  • Verification IP, Memory Models and Design IP’s

    Organizations: EDAC, GSA, EIC, OCP-IP, Si2, SPIRIT SmartDV offers wide range of Verification IP’s, Memory models and Design IP’s. Verification models include complete MIPI protocol

  • Mixel’s MIPI M-PHY

    Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI® Alliance Specfication for M-PHY®. The IP

  • PLL and DLL Hard Macros

    Organizations: GSA True Circuits’ complete family of standardized, silicon-proven, low-jitter PLL and DLL hard macros spans nearly all performance points and features typically

  • Calypto PowerPro Product Family

    With the explosion of consumer electronics, designing for low-power has become an important design constraint and a key differentiating factor. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, both via automated tools as well as manually by the RTL designers.