Chip Design Resource Center

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From the Blogosphere

  • Cisco to absorb smart-memory IP

    Cisco has decided to buy memory-controller specialist Memoir Systems and absorb the technology into its Insieme business unit, which specializes in data-center switch technologies, a move that underlines the issues facing small IP suppliers and their customers....

  • Blog Post: How design your system like a true pirate engineer

    Yar Mateys! I’ve been told today is “Pirate Appreciation Day,” or as you land lubbers call it, “Talk Like a Pirate Day.”  A day where all those who sail the seven seas stop and raise a mug of grog and appreciate all the hard work thar be into being a pirate.  What’s that you...

  • What is the second redirect for?

    My ws0 is trying to ping 10.xx.2.1 and doesnt have an arp cache. I understand what the first redirect is for since my BR is sending the ws0 to look for that ip at R3, what is the second redirect for?...

  • Portable and Productive Test Creation with Graph-Based Stimulus

    Verification engineers spend lots of time creating tests. In fact, creating enough tests to verify the design functionality consistently tops the list of verification challenges, according to periodic surveys of our customers. One challenge in test creation is that verification occurs in multiple environments. For high-level...

Featured Articles

Featured Products

  • Mixel’s MIPI M-PHY

    Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI® Alliance Specification for M-PHY®. The

  • IDesignSpec™

    IDesignSpec™ is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically generate

  • Expert SystemVerilog and UVM Training Services

    Founded in 1992, Sutherland HDL has trained thousands of engineers throughout the world on Verilog, SystemVerilog, SVA and UVM. WORKSHOP HIGHLIGHTS Verilog and SystemVerilog

  • VTRAN Vector Translation Tool

    With nearly 25 years of field-proven success, VTRAN™ offers the most cost-effective, full-feature solution to creating EDA and ATE test programs from simulation and ATPG vectors.

  • IDesignSpec™

    IDesignSpec™is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically generate

  • Meridian CDC

    Meridian CDC is the fastest, highest capacity and most precise clock domain crossing (CDC) solution in the market. It performs comprehensive structural and functional analysis to ensure

  • DDR 4/3 PHY

    Organizations: GSA The TCI DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually,