Chip Design Resource Center

From the Blogosphere

  • ARM DesignStart case study demonstrates scheme’s ease-of-use

    ARM and Mentor describe a proof-of-concept project using free tools and IP to combine AMS and digital....

  • Passwords: How Even Your Bank Doesn't Know Your PIN

    In my predictions for 2018 piece yesterday, Nibbles: Breakfast Bytes Predictions for 2018 , I wrote: The first amazing thing about this is that even when I was studying computer science back in stone age, before PCs and smartphones and the internet, Roger Needham, my lecturer on operating systems told us that passwords...

  • Passwords: How Even Your Bank Doesn't Know Your PIN

    In my predictions for 2018 piece yesterday, Nibbles: Breakfast Bytes Predictions for 2018 , I wrote: The first amazing thing about this is that even when I was studying computer science back in stone age, before PCs and smartphones and the internet, Roger Needham, my lecturer on operating systems told us that passwords...

  • Passwords: How Even Your Bank Doesn't Know Your PIN

    In my predictions for 2018 piece yesterday, Nibbles: Breakfast Bytes Predictions for 2018 , I wrote: The first amazing thing about this is that even when I was studying computer science back in stone age, before PCs and smartphones and the internet, Roger Needham, my lecturer on operating systems told us that passwords...

Featured Articles

  • Hail a Cab and All Hail the GPU

    The autonomous car will rely on data that has to be processed in real-time and adapt through machine learning for safe passage whatever the conditions. Autonomous vehicles will rely

  • IEDM 2017: Intel’s 10nm Platform Process

    IEDM this year was its usual mixture of academic exotica and industrial pragmatica (to use a very broad-brush description), but the committee chose to keep us all waiting until the

  • The Future of Healthcare May Reside in Your Smart Clothes

    When most people think of wearables, they often think of the obligatory smart watches, fitness monitors, and heart rate monitors that are typically worn on the wrist or. However, the

  • What the Future of LiDAR Looks Like

    Autonomous cars by 2020 is a good bet—as long as goals across five key criteria are met. The LiDAR market is approaching a tipping point of mass market adoption that spans from individual

  • WYSIWYG for the Automotive AR Era: Q&A with Mike Firth Texas Instruments

    Why HUD system imagery and drivers stand to gain Editor’s Note: Automotive Head-Up Displays (HUDs) enable drivers to see critical information in front of their eyes so they

  • IEDM 2017: Intel’s 10nm Platform Process

    IEDM this year was its usual mixture of academic exotica and industrial pragmatica (to use a very broad-brush description), but the committee chose to keep us all waiting until the

  • Developing Heterogeneous Cache Coherent SoCs

    Automotive and other customer needs are not what they once were. As with other challenges, the task of successfully developing heterogeneous cache coherent SoCs demands an understanding

  • A Personal Assistant At Your Side

    Imec proximity technology can open doors for you, take you to the right floor, configure your room with preferred lighting and temperature, remember your fitness scheme and more.

Featured Products

  • Mixel’s MIPI D-PHY RX+

    Organizations: GSA, MIPI Alliance D-PHY RX+ is a CSI and DSI D-PHY Receiver optimized for small area and low power, while achieving full-speed production testing, in-system testing,

  • Mixel’s MIPI C-PHY/D-PHY Combo

    Organizations: GSA, MIPI Alliance Mixel’s MIPI C-PHY/D-PHY Combo is a high-frequency low-power, low-cost, source-synchronous, physical layer. The PHY can be configured as a MIPI

  • Timing Constraints - Done Once! Done Right!

    Organizations: EDAC, GSA, Si2 Constraints-Manager (ConMan), Constraints-Certifier (ConCert), Exceptions Toolbox and Clock Domain Crossing Review (ConDor) End to End timing constraints

  • SOS Design Data & IP Management Platform

    ClioSoft ClioSoft’s SOS Design Collaboration Platform is built to handle the complex requirements of system-on-chip design flows. The SOS platform provides a sophisticated multi-site

  • Industry Leading Tools Linking Simulation and ATPG to Test

    Source III provides the industry’s most comprehensive and cost-effective vector translation product (VTRAN®) which links simulation/ATPG vector data to ATE, a powerful vector analysis

  • Mixel’s MIPI M-PHY

    Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI® Alliance Specification for M-PHY®. The

  • IDesignSpec™

    IDesignSpec™ is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically generate

  • IDesignSpec™

    IDesignSpec™is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically generate

Chip Design Datasheet Directory

    EDA Tools

    Verification Functional

  • by AMIQ EDA

    Design and Verification Tools (DVT) is an integrated development environment (IDE) for the e language, SystemVerilog, Verilog, and VHDL. It helps design and verification engineers...

  • by AMIQ EDA

    Thorough audit of your test benches Verissimo SystemVerilog Testbench Linter is a static code analysis tool that allows engineers to perform a thorough audit of their testbenches....

  • Methods / EDA Tools

  • by ClioSoft Inc.

    ClioSoft ClioSoft’s SOS Design Collaboration Platform is built to handle the complex requirements of system-on-chip design flows. The SOS platform provides a sophisticated multi-site...

  • Design-for-Test (DFT)

  • by Source III, Inc.

    Source III provides the industry’s most comprehensive and cost-effective vector translation product (VTRAN®) which links simulation/ATPG vector data to ATE, a powerful vector...

  • by Source III, Inc.

    With nearly 25 years of field-proven success, VTRAN™ offers the most cost-effective, full-feature solution to creating EDA and ATE test programs from simulation and ATPG vectors....

  • Verification

  • by Agnisys

    IDesignSpec™is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically...

  • by Agnisys

    IDesignSpec™ is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically...

  • by Excellicon

    Organizations: EDAC, GSA, Si2 Constraints-Manager (ConMan), Constraints-Certifier (ConCert), Exceptions Toolbox and Clock Domain Crossing Review (ConDor) End to End timing...

  • by Real Intent

    Meridian CDC is the fastest, highest capacity and most precise clock domain crossing (CDC) solution in the market. It performs comprehensive structural and functional analysis...

  • by Sutherland HDL, Inc

    Founded in 1992, Sutherland HDL has trained thousands of engineers throughout the world on Verilog, SystemVerilog, SVA and UVM. WORKSHOP HIGHLIGHTS Verilog and SystemVerilog...

  • Semiconductor Technologies

    IP - Core

  • by Calypto Design Systems

    Accelerate Time to Rtl, Reduce Verification Effort
    The Catapult® high-level synthesis tool empowers designers to use industry standard ANSI C++ and SystemC to describe functional intent, and move up to a more productive abstraction level.

  • by Calypto Design Systems

    With the explosion of consumer electronics, designing for low-power has become an important design constraint and a key differentiating factor. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, both via automated tools as well as manually by the RTL designers.

  • by Calypto Design Systems

    The emergence of consumer electronics is causing a fundamental shift in Register Transfer Level (RTL) design methodologies. The race for time to market has resulted in the adoption and growth of higher level design creation methodologies. In particular, High Level Synthesis (HLS) directly from software models to hardware has become very popular.

  • by Mixel, Inc.

    Organizations: GSA, MIPI Alliance Mixel’s MIPI C-PHY/D-PHY Combo is a high-frequency low-power, low-cost, source-synchronous, physical layer. The PHY can be configured as...

  • by Mixel, Inc.

    Organizations: GSA, MIPI Alliance D-PHY RX+ is a CSI and DSI D-PHY Receiver optimized for small area and low power, while achieving full-speed production testing, in-system...

  • by Mixel, Inc.

    Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI® Alliance Specification for M-PHY®....

  • by SmartDV Technologies India Private Limited

    Organizations: EDAC, GSA, EIC, OCP-IP, Si2, SPIRIT SmartDV offers wide range of Verification IP’s, Memory models and Design IP’s. Verification models include complete...

  • by True Circuits Inc.

    Organizations: GSA The TCI DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually,...

  • by True Circuits Inc.

    Organizations: GSA True Circuits’ complete family of standardized, silicon-proven, low-jitter PLL and DLL hard macros spans nearly all performance points and features typically...