Chip Design Resource Center

From the Blogosphere

  • Blog Post: Designing output isolated 4-wire sensor transmitters

    In my last post , I discussed the basic structure of 4-wire sensor transmitters and how they differ from 2-wire and 3-wire sensor transmitters. In this post, I will discuss the construction of a locally powered output-isolated 4-wire sensor transmitter like the one shown in Figure 1. Locally powered 4-wire sensor transmitters...

  • Ready for a Verification Extravaganza in the Land of Verification Engineers?

    I have always been wanting to contribute to the growing verification engineering community in India, which Mentor’s CEO Wally Rhines calls “the largest verification market in the world”. So when I first accompanied the affable Dennis Brophy to the IEEE India office back in April of 2014 to discuss the possibility...

  • EEVblog #774 – Low Battery Discharge Testing Part 1

    Dave shows how to do discharge testing on AAA and AA alkaline batteries, for the specific purpose of investigating how much energy is left under the industry standard 0.8V cutout voltage. This is an explanation of the test setup, verification, and a sample plot of some data before the long term testing. The setup consists...

  • Cadence IP for USB Works over Type-C (Proof Inside)

    There is no other specification in the history of USB that caused so much discussion and interest as the USB Type-C. The new type of connector, designed to be a jack of all trades, eliminates all flaws of legacy Type-A and Type-B plugs, and adds significant benefits for USB and beyond. Here's a brief rundown of those...

Featured Articles

  • Comparison 1Y nanometer NAND architecture and beyond

    A few years ago, some of the semiconductor process and device analysts thought 2D planar NAND Flash would soon be coming to an end due to the scaling limits, especially around the 20nm

  • Manage Giga-Gate Testing Hierarchically

    The benefits of hierarchical test include reduction of test time, reduction of automatic test pattern generation (ATPG) run time, better management of design and integration tasks, and moving DFT insertion and pattern generation much earlier in the design process.

  • Q&A with ARM: Securing the IoT using ARM Cortex Processors, and a growing mbed platform suite

    ARM’s holistic approach to securing the IoT balances architecture, mbed OS and new software that’s perfect for connected devices.

  • Computing at the Edge

    As the number of devices at the edge of the network cloud continues to grow, more processing is needed to handle the huge quantities edge-connected data.

    This is a collection of questions posed to ARM over the past couple of months; ARM's answers—attributed to the company's Ian Johnson, Senior Product Manager—are an excellent "quick read" ARM's recent IoT infrastructure initiative, and on Cortex-M7 processor.

  • Freescale Adds to ARM Cores in SoCs to Protect the Mobile IoT

    Freescale Semiconductor has added three applications processors to its i.MX series, addressing security and power performance for the connected, mobile devices that proliferate in the Internet of Things (IoT).

  • "Contextual Sensing" is Another IoT Area for ARM

    Convincing sensor vendors to add smarts to their devices and take a systems approach will provide context to IoT devices and give ARM two new growth areas.

  • USB Type-C: Doing Away with a Difference Makes a Difference

    A connector technology that does away with a source of consumer frustration will invigorate the industrial, smartphones/tablets, automotive and other markets, too. With a traditional

  • The Odd Couple - Analog IPs and Design Data Management

    Design engineers used to call mixed-signal chips “big D/little A” for their high digital content paired with a small analog portion. However, the balance of power is changing with

Featured Products

  • SOS Design Data & IP Management Platform

    ClioSoft ClioSoft’s SOS Design Collaboration Platform is built to handle the complex requirements of system-on-chip design flows. The SOS platform provides a sophisticated multi-site

  • Industry Leading Tools Linking Simulation and ATPG to Test

    Source III provides the industry’s most comprehensive and cost-effective vector translation product (VTRAN®) which links simulation/ATPG vector data to ATE, a powerful vector analysis

  • IDesignSpec™

    IDesignSpec™ is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically generate

  • Mixel’s MIPI M-PHY

    Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI® Alliance Specification for M-PHY®. The

  • IDesignSpec™

    IDesignSpec™is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically generate

  • Meridian CDC

    Meridian CDC is the fastest, highest capacity and most precise clock domain crossing (CDC) solution in the market. It performs comprehensive structural and functional analysis to ensure

  • VTRAN Vector Translation Tool

    With nearly 25 years of field-proven success, VTRAN™ offers the most cost-effective, full-feature solution to creating EDA and ATE test programs from simulation and ATPG vectors.

Chip Design Datasheet Directory

    EDA Tools

    Verification Functional

  • by AMIQ EDA

    Design and Verification Tools (DVT) is an integrated development environment (IDE) for the e language, SystemVerilog, Verilog, and VHDL. It helps design and verification engineers...

  • by AMIQ EDA

    Thorough audit of your test benches Verissimo SystemVerilog Testbench Linter is a static code analysis tool that allows engineers to perform a thorough audit of their testbenches....

  • Methods / EDA Tools

  • by ClioSoft Inc.

    ClioSoft ClioSoft’s SOS Design Collaboration Platform is built to handle the complex requirements of system-on-chip design flows. The SOS platform provides a sophisticated multi-site...

  • Design-for-Test (DFT)

  • by Source III, Inc.

    Source III provides the industry’s most comprehensive and cost-effective vector translation product (VTRAN®) which links simulation/ATPG vector data to ATE, a powerful vector...

  • by Source III, Inc.

    With nearly 25 years of field-proven success, VTRAN™ offers the most cost-effective, full-feature solution to creating EDA and ATE test programs from simulation and ATPG vectors....

  • Verification

  • by Agnisys

    IDesignSpec™is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically...

  • by Agnisys

    IDesignSpec™ is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically...

  • by Real Intent

    Meridian CDC is the fastest, highest capacity and most precise clock domain crossing (CDC) solution in the market. It performs comprehensive structural and functional analysis...

  • by Sutherland HDL, Inc

    Founded in 1992, Sutherland HDL has trained thousands of engineers throughout the world on Verilog, SystemVerilog, SVA and UVM. WORKSHOP HIGHLIGHTS Verilog and SystemVerilog...

  • Semiconductor Technologies

    IP - Core

  • by Calypto Design Systems

    Accelerate Time to Rtl, Reduce Verification Effort
    The Catapult® high-level synthesis tool empowers designers to use industry standard ANSI C++ and SystemC to describe functional intent, and move up to a more productive abstraction level.

  • by Calypto Design Systems

    With the explosion of consumer electronics, designing for low-power has become an important design constraint and a key differentiating factor. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, both via automated tools as well as manually by the RTL designers.

  • by Calypto Design Systems

    The emergence of consumer electronics is causing a fundamental shift in Register Transfer Level (RTL) design methodologies. The race for time to market has resulted in the adoption and growth of higher level design creation methodologies. In particular, High Level Synthesis (HLS) directly from software models to hardware has become very popular.

  • by Mixel, Inc.

    Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI® Alliance Specification for M-PHY®....

  • by SmartDV Technologies India Private Limited

    Organizations: EDAC, GSA, EIC, OCP-IP, Si2, SPIRIT SmartDV offers wide range of Verification IP’s, Memory models and Design IP’s. Verification models include complete...

  • by True Circuits Inc.

    Organizations: GSA The TCI DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually,...

  • by True Circuits Inc.

    Organizations: GSA True Circuits’ complete family of standardized, silicon-proven, low-jitter PLL and DLL hard macros spans nearly all performance points and features typically...