Chip Design Resource Center

Top Stories and News

more

From the Blogosphere

  • Aeroflex, Sequans Demonstrate LTE Cat 4 Throughput at CTIA

    This week at the International CTIA Wireless 2012 in New Orleans, 4G chip maker Sequans Communications, in collaboration with test instruments supplier Aeroflex conducted a live LTE throughput demonstration at the Sequans’ booth. The maker claims that it is one … Continue reading →...

    RF/Microwave Tracker

  • For System-Level Verification, Cooperation Beats Competition

    By Frank Schirrmeister Maintaining system-level verification at various levels of abstraction is a costly time sink. Much better is a verification environment that encompasses the electronic system level, SystemC, SystemVerilog, and RTL....

    Electronics Design Articles

  • CDNLive! EMEA 2012 to Take Place in Munich, Germany from 14-16 May

    Cadence Design Systems will hold the CDNLive! EMEA user conference from May 14-16 at the Dolce Hotel in Munich/Unterschleissheim. The annual user conference will share fresh new and best practices that address all aspects of design and IP creation, integration, and verification. Attendees of CDNLive! EMEA will get to explore...

    EDA Blog

  • Real Intent Helps Designers Verify Intent

    A little over a month ago, Vaishnav Gorur of Real Intent published an article on Tech Forum with the title "Blindsided by a Glitch". The article provides good design guidelines while pointing out that following the guidelines is not always sufficient to avoid downstream problems. The article made me think about how dependent...

    Gabe On EDA
    • more

Featured Articles

  • Fast and New Method for Cycle Slip Analysis in PLL: Part 1

    This article presents a fast and new approach to analyzing cycle slip in a phase-locked loop (PLL) with a saw tooth phase detector. PLL cycle slip analysis is a nonlinear and mathematical hand calculation is perceived to be complex. In most cases, powerful CAD software, such as Agilent Technologies’ Advanced Design System (ADS), is relied on to do the simulation, as it outputs accurate and reliable data. However, this article will elaborate on how cycle slip occurs and what actually happens during cycle slip. Linear analysis, such as Laplace and inverse Laplace transform, are used to analyze the time domain response between cycle slipping. One caveat is that strict conditions must be applied for the analysis to be accurate. Although this is the case, this analysis will give new perspective and thus will help one achieve a more intuitive, solid understanding as to why and what happens during cycle slip. Analysis results from this simple approach with different input conditions will be compared with accurate output from ADS.

  • The Next Big Challenge

    The path forward may be more focused on matching goals at the architectural stage, and then being able to swap information as a design progresses. Software is the next big target in

  • Analyst: EUV Misses 14nm Node and Now Aims for 10nm

    Can EUV maintain viability and live up to promises? Extreme ultraviolet (EUV) lithography has missed the 20nm — and the 14nm — process nodes, according to an analyst, who added

  • Can Data Mining Remove the Jeopardy from Design Decisions?

    Predicting design flow outcomes can push chip design forward I’ve recently compared EDA to other industries and have wondered, “What does EDA have in common with network security?”

  • GlobalFoundries, Mentor Team Up on Yield Front

    Chip design and process costs continue to soar Chip design and process technology costs continue to escalate at an alarming rate for each node. The combined cost for a new chip design

  • Model Report Card

    STMicroelectronics reveals overall model approach, transactor needs and issues with processor models or IP models From its perspective as a leader implementing system level design

  • Nanometer-SPICE Verification Meta-Model Looks from Past to Future

    “He who controls the spice controls the universe.”—Baron Harkonnen (Dune) During the week between Christmas and New Year’s Day, I generally take off and catch up on things

  • Experts At The Table: Changing Design

    Time to market is the major differentiator System-Level Design sat down to discuss the changing design landscape with Juan Rey, senior director of engineering for Calibre in Mentor

  • Panel: Analog Scaling Requires New Design Techniques

    Disconnect Seen for Mixed-signal Chip Design Moore’s Law is showing no signs of slowing down, but there are issues in the development of new mixed-signal designs: Analog is falling

  • SPIE Panel: Time is Ripe for Alternative NGLs

    DSA appears to be the darling in the NGL race The IC industry needs to think differently about lithography, according to a panel at the SPIE Advanced Lithography conference in San

more

Featured Products

  • nVS family of Verification IPs

    nSys Verification Suite (nVS) family is the world’s largest portfolio of Verification IPs. Hundreds of ASIC/FPGA developers worldwide are using the nVS (nSys Verification Suite)

  • ALVAFE10X4-165M40THLA

    Organizations: GSA The ALVAFE10X4-165M40THLA is a 4-channel ultra-compact and very low power video analog-front-end (VAFE) silicon IP implemented in 40 nm LP Process. The IP includes

  • PLL and DLL Hard Macros

    Organizations: GSA True Circuits’ complete family of standardized, siliconproven, low-jitter PLL and DLL hard macros spans nearly all performance points and features typically requested

  • Expert SystemVerilog Training Service

    Founded in 1992, Sutherland HDL has trained thousands of engineers throughout the world. Sutherland HDL SystemVerilog training workshops are developed and presented by engineering

Chip Design Datasheet Directory