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SmartFusion2 Lowest Power FPGAs
Kintex 7 FPGA family: High Performance DDR3 memory throughput achieved by optimization of the memory controller
Write Assist in Low-Voltage SRAMs
Enea Element®: Simplify Distributed Systems with Frameworks from Enea Element
Redefining RF and Microwave Instrumentation Through Open Software and Modular Hardware
VPX for High-Performance Avionic Computers
OpenVPX System Bandwidth: A comparison of 10Gb Ethernet Performance, Serial Rapid IO, and InfiniBand
Docea Power to present unique solutions for modelling and simulation of dynamic thermal management strategies at DAC
Docea Power, the design for low power company that delivers software solutions for power and thermal analysis at the architectural level , will exhibit at the 50 th Design Automation
ProximusDA Teams with STMicroelectronics to Develop Next-Generation Distributed SOC TLM Virtual Prototypes
Avery Design Systems Enhances RTL and Gate-Level X-Verification with SimXACT 2.0 and XOPT 2.0
Si2 Announces DAC Booth Presentations
Jedat Releases Innovative OA-based Circuit and Layout Tools for Analog Mixed-Signal Designs at DAC 2013
TSMC Certifies Cadence Tempus Timing Signoff Solution for 20nm Designs
Mentor Graphics Teams with OpSIS Foundries and Lumerical Solutions on PDK Development for IME Silicon Photonics Process
Atrenta Presents RTL Signoff at 50th DAC
Si2 Announces Board of Directors for 2013-2014
ON Semiconductor Awarded Title III Government Funding for Development of Advanced Next-Generation Star Tracker Image Sensor
Featured Articles
Enabling Accurate Glucose Measurement
Designing a glucose monitoring device is made easy with an 8-bit, 8051-based Programmable SoC
Practical Applications of Cloud Computing in Semiconductor Chip Design
Cloud computing will play an increasingly significant role in FPGA designs because the benefits to designers are tremendous. Chip design engineers face a myriad of challenges in
Fundamental Laws of (FPGA) Nature: Similar, Yet Different
Lattice and Xilinx muse on parallelism, partial reconfigurability, and the state-of-the-art in IP and EDA tools.
Tackling the Challenge of Building Smaller, Lighter, and More Efficient Component-based Avionics with CFD
Computational Fluid Dynamics software helps defense systems designers doubly: it aids in optimizing component SWaP, and models device thermal behavior across time and vendors.
Dialing the Right Designs for Mobile Accessories
What are the new technologies in the arena?
PCIe Follows USB 3.0 to Mobile Applications
PCIe is following USB into mobile chip-to-chip applications by adopting the low-power MIPI M-PHY.
ARM Tips Strategy to Crack Server Market
IP giant also talks about Intel, finFETs and the cloud Needless to say, ARM Holdings is the dominate supplier of processor intellectual property (IP) in the booming cell-phone
Early Integration Gains Steam
A subtle but important shift is under way inside of EDA. While vendors are still focused on solving some thorny issues at the front end of Moore’s Law, much of the R&D effort
Free Hardware and Software but not IP
Will the success of the open source movement in software and even hardware cause changes in silicon IP business models?
Wanted: New Memory Type for Supercomputing
The shift towards a new class of exascale computers will require new breakthroughs in power management and chip-level technologies like memories, according to a technologist at an event
Featured Products

PLL and DLL Hard Macros
Organizations: GSA True Circuits’ complete family of standardized, silicon-proven, low-jitter PLL and DLL hard macros spans nearly all performance points and features typically

Calypto PowerPro Product Family
With the explosion of consumer electronics, designing for low-power has become an important design constraint and a key differentiating factor. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, both via automated tools as well as manually by the RTL designers.

Calypto SLEC Product Family
The emergence of consumer electronics is causing a fundamental shift in Register Transfer Level (RTL) design methodologies. The race for time to market has resulted in the adoption and growth of higher level design creation methodologies. In particular, High Level Synthesis (HLS) directly from software models to hardware has become very popular.

Calypto Catapult Product Family
Accelerate Time to Rtl, Reduce Verification Effort
The Catapult® high-level synthesis tool empowers designers to use industry standard ANSI C++ and SystemC to describe functional intent, and move up to a more productive abstraction level.










