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Hardent Inc. introduces the first real-time video compression intellectual property (IP) technology that is VESA Display Stream Compression (DSC)-compliant. This decoder will facilitate
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But I received this message:Registration denied, this forum runs an active policy of not allowing spammers. Please contact us via the Contact Us page link if you believe this is in error.I never spammed any one since it's a waste of time.My IP is not black listed on honey pot ......
You may have noticed, (I hope at least), that I haven’t written here in a while. Here’s why. In January, we went camping during a sunny yet cool weekend in Sommerville, TX. It was nice to get outside and to … Continue reading →...
Flower Technology and EnSilica collaborate on ASIC mining solutions for cryptocurrencies like Bitcoin
Bitcoin and other cryptocurrencies that are based on scrypt hashing algorithms (Lifecoin, Auroracoin, Dogecoin, and Mastercoin) are on the rise. Scrypt-based cryptocurrency ASIC mining solution start-up Flower Technologies and eSi-RISC soft processor core and encryption and peripherals company EnSilica have partnered to...
According to the World Health Organization (WHO), more than 1.2 million people die as a result of a road traffic crash each year worldwide, and as many as 50 million are injured. Most of these tragedies can be attributed to human error. From speeding, drinking and driving and distracted driving, many of these accidents...
Initiated by Apple’s launch of the iPhone, the subsequent explosive growth of the smartphone market has provided the MEMS industry with one of its biggest opportunities to supply
Should foundries establish and share best practices to manage sub-nanometer effects to improve yield and also manufacturability? Team effort Design for yield (DFY) has been referred
Today's always-on, cloud-connected electronic products create value by delivering massive amounts of data on time to serve a wide variety of applications. Whether streaming video, transacting
Projected growth in the third-party semiconductor intellectual-property (IP) market through 2017 may affect the direction and evolution of subsystem designs.
Earlier warnings by Berkeley's Dr. Rabaey are echoed in ARM-Economist report.
While 6 billion people know about USB on the outside of smartphones, cameras, and laptops, only product designers are familiar with how USB is used inside of these products. In laptops, for example, the touchpad, webcam, and broadband modem often use standard USB parts—consuming standard USB power—internally.
I recently had lunch with a dejected engineer from a semiconductor startup in big trouble. After months of effort at no small expense, the chip design project was an utter failure,
Power impact is greatest above the gate level
In Part II, IP Extreme’s Savage reveals why IP standards take so long while discussing brand values, macro trends, and changes wrought by patent trolls.
Definitions vary but implications for the Internet of Things does not.
Meridian CDC is the fastest, highest capacity and most precise clock domain crossing (CDC) solution in the market. It performs comprehensive structural and functional analysis to ensure
Design and Verification Tools (DVT) is an integrated development environment (IDE) for the e language, SystemVerilog, Verilog, and VHDL. It helps design and verification engineers
Organizations: GSA The TCI DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually,
Organizations: EDAC, GSA, EIC, OCP-IP, Si2, SPIRIT SmartDV offers wide range of Verification IP’s, Memory models and Design IP’s. Verification models include complete MIPI protocol
Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI® Alliance Specfication for M-PHY®. The IP
Organizations: GSA True Circuits’ complete family of standardized, silicon-proven, low-jitter PLL and DLL hard macros spans nearly all performance points and features typically
With the explosion of consumer electronics, designing for low-power has become an important design constraint and a key differentiating factor. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, both via automated tools as well as manually by the RTL designers.