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Designing with FPGAs for Embedded Computing Speed and Flexibility
SmartFusion2 Lowest Power FPGAs
Kintex 7 FPGA family: High Performance DDR3 memory throughput achieved by optimization of the memory controller
Write Assist in Low-Voltage SRAMs
Enea Element®: Simplify Distributed Systems with Frameworks from Enea Element
Redefining RF and Microwave Instrumentation Through Open Software and Modular Hardware
VPX for High-Performance Avionic Computers
VeriSilicon Introduces Hantro G2 Video Decoder IP with HEVC and VP9 Support
World’s first semiconductor IP to support both HEVC and VP9 video formats VeriSilicon Holdings Co., Ltd. (VeriSilicon), a leading custom silicon solutions and semiconductor
Microsemi Broadens FPGA Product Portfolio with Highly-integrated IGLOO2
Micrium Announces Support of Microsemi's New SmartFusion2 SoC FPGAs
eMemory Technology Selects Berkeley Design Automation Analog FastSPICE™ Platform for Embedded Non-Volatile Memory
Real Intent Delivers Next Release of Meridian CDC for Clock Domain Crossing Sign-off of SOC Designs
AMD Unveils Server Strategy and Roadmap
Cavium’s New OCTEON III family of processors feature latest Imagination Technologies MIPSr5 architecture
Extension Media Creates Content Marketing Services Group Headed by Technology Media Veteran Chris A. Ciufo
Rockchip Launches New Tablet SoCs on GLOBALFOUNDRIES' 28nm HKMG Process Technology
ON Semiconductor and Airbus Complete Collaborative Development of Complex ASIC for A350 XWB Flight Control Computer
Featured Articles
AWR’s Sherry Hess Tapped to Co-Chair IEEE MTT-S Women in Engineering Organization
AWR Corporation, the innovation leader in high-frequency EDA software, is proud to announce that Sherry Hess, vice president of marketing and long time advocate for women in engineering,
Dialing the Right Designs for Mobile Accessories
What are the new technologies in the arena?
PCIe Follows USB 3.0 to Mobile Applications
PCIe is following USB into mobile chip-to-chip applications by adopting the low-power MIPI M-PHY.
ARM Tips Strategy to Crack Server Market
IP giant also talks about Intel, finFETs and the cloud Needless to say, ARM Holdings is the dominate supplier of processor intellectual property (IP) in the booming cell-phone
Enabling Accurate Glucose Measurement
Designing a glucose monitoring device is made easy with an 8-bit, 8051-based Programmable SoC
Practical Applications of Cloud Computing in Semiconductor Chip Design
Cloud computing will play an increasingly significant role in FPGA designs because the benefits to designers are tremendous. Chip design engineers face a myriad of challenges in
Fundamental Laws of (FPGA) Nature: Similar, Yet Different
Lattice and Xilinx muse on parallelism, partial reconfigurability, and the state-of-the-art in IP and EDA tools.
Tackling the Challenge of Building Smaller, Lighter, and More Efficient Component-based Avionics with CFD
Computational Fluid Dynamics software helps defense systems designers doubly: it aids in optimizing component SWaP, and models device thermal behavior across time and vendors.
Early Integration Gains Steam
A subtle but important shift is under way inside of EDA. While vendors are still focused on solving some thorny issues at the front end of Moore’s Law, much of the R&D effort
Free Hardware and Software but not IP
Will the success of the open source movement in software and even hardware cause changes in silicon IP business models?
Featured Products
PLL and DLL Hard Macros
Organizations: GSA True Circuits’ complete family of standardized, silicon-proven, low-jitter PLL and DLL hard macros spans nearly all performance points and features typically
Calypto PowerPro Product Family
With the explosion of consumer electronics, designing for low-power has become an important design constraint and a key differentiating factor. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, both via automated tools as well as manually by the RTL designers.
Calypto SLEC Product Family
The emergence of consumer electronics is causing a fundamental shift in Register Transfer Level (RTL) design methodologies. The race for time to market has resulted in the adoption and growth of higher level design creation methodologies. In particular, High Level Synthesis (HLS) directly from software models to hardware has become very popular.
Calypto Catapult Product Family
Accelerate Time to Rtl, Reduce Verification Effort
The Catapult® high-level synthesis tool empowers designers to use industry standard ANSI C++ and SystemC to describe functional intent, and move up to a more productive abstraction level.
Chip Design Datasheet Directory
Semiconductor Technologies
IP - Core
Blogs
The Canonical Hamiltonian
Snooping on Planes from Space!
Hot on the heels of recent NSA revelations, the European Space Agency announced today[1] that they’ve...
JB’s Circuit
Chris A. Ciufo on All Things Embedded
Does Altera Have “Big Data” Communications on the Brain?
In wireless, wireline and financial “big data” applications, moving all those packets needs...
Chipnastics
New Processor Core Options Try Some ARM Wrestling
When designing a system on a chip (SoC) that employs one or more embedded processor cores, the choice...
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EECatalog Tech Videos
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Featured Solutions
Calypto Catapult Product Family
Accelerate Time to Rtl, Reduce Verification Effort
The Catapult® high-level synthesis tool empowers designers to use industry
standard ANSI C++ and SystemC to describe functional intent, and move up to a more productive abstraction level.
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