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From the Blogosphere

  • Cadence targets ISO 26262 with verification support

    Cadence Design Systems has built a verification environment around its vManager software for ICs and systems that need to conform to the ISO 26262 safety standard....

  • Blog Post: Enabling safer roads for all vehicles

    Brooke Williams doesn’t have to look far to find inspiration for his work on the TDA3x automotive system on a chip (SoC) family used in advanced driver assistance systems (ADAS). The business manager for ADAS just glances at the picture frames on his desk. “I have three kids who are not yet driving, but one...

  • Diging Inside the TCP/IP packets

    Hi there, I am working on signature based IDS, for this I have captured the TCP/IP traffic through Wireshark and got a pcap file, I want to extract some fields from the packet itself. How do I do this? I have been searching through the Internet and got the idea ......

  • e and SystemVerilog: The Ultimate Race

    For years we've watched the e and SystemVerilog race via countless presentations, articles, and blogs. Each language is applied to SoC verification yet the differences are well documented so any comparison is subject to recoding from one language to the other. This makes a direct performance comparison difficult to...

Featured Articles

Featured Products

  • Mixel’s MIPI M-PHY

    Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI® Alliance Specification for M-PHY®. The

  • IDesignSpec™

    IDesignSpec™ is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically generate

  • Expert SystemVerilog and UVM Training Services

    Founded in 1992, Sutherland HDL has trained thousands of engineers throughout the world on Verilog, SystemVerilog, SVA and UVM. WORKSHOP HIGHLIGHTS Verilog and SystemVerilog

  • VTRAN Vector Translation Tool

    With nearly 25 years of field-proven success, VTRAN™ offers the most cost-effective, full-feature solution to creating EDA and ATE test programs from simulation and ATPG vectors.

  • IDesignSpec™

    IDesignSpec™is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically generate

  • Meridian CDC

    Meridian CDC is the fastest, highest capacity and most precise clock domain crossing (CDC) solution in the market. It performs comprehensive structural and functional analysis to ensure

  • DDR 4/3 PHY

    Organizations: GSA The TCI DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually,