Chip Design Resource Center

From the Blogosphere

  • Blog Post: Select the correct PMBus POL solution for your application

    Do you need to monitor system operation or collect data about the power supply? If the answer is yes, then PMBus is for you. PMBus is an industry-standard protocol that facilitates 2-wire digital communication with power converters and other devices in a power system. Using PMBus in your system increases power density and...

  • EEVblog #774 – Low Battery Discharge Testing Part 1

    Dave shows how to do discharge testing on AAA and AA alkaline batteries, for the specific purpose of investigating how much energy is left under the industry standard 0.8V cutout voltage. This is an explanation of the test setup, verification, and a sample plot of some data before the long term testing. The setup consists...

  • UVM: The Next IEEE Standard (1800.2)

    Accellera Handoffs UVM to IEEE It has been a long path from Mentor’s AVM to IEEE P1800.2.  But the moment has arrived: Accellera has formally announced UVM 1.2 will be submitted as a contribution to the IEEE P1800.2™ working group. Verification Methodology Beginnings As the IEEE finalized approval of the initial release...

  • 10nm flow reveals complexity of finFET design process

    Collaboration between ARM, TSMC and Synopsys reveals challenges of 10nm finFET design flows....

Featured Articles

Featured Products

  • Advantech MIC-5342 Telecom Blade

    Compatible Operating Systems: Red Hat, CentOS, Wind River, 6WINDGate Specification Compliance: PICMG ATCA The MIC-5342 is based on the Intel® platform formerly codenamed "River

  • SOS Design Data & IP Management Platform

    ClioSoft ClioSoft’s SOS Design Collaboration Platform is built to handle the complex requirements of system-on-chip design flows. The SOS platform provides a sophisticated multi-site

  • Industry Leading Tools Linking Simulation and ATPG to Test

    Source III provides the industry’s most comprehensive and cost-effective vector translation product (VTRAN®) which links simulation/ATPG vector data to ATE, a powerful vector analysis

  • Mixel’s MIPI M-PHY

    Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI® Alliance Specification for M-PHY®. The

  • IDesignSpec™

    IDesignSpec™ is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically generate

  • Meridian CDC

    Meridian CDC is the fastest, highest capacity and most precise clock domain crossing (CDC) solution in the market. It performs comprehensive structural and functional analysis to ensure

  • VTRAN Vector Translation Tool

    With nearly 25 years of field-proven success, VTRAN™ offers the most cost-effective, full-feature solution to creating EDA and ATE test programs from simulation and ATPG vectors.

Chip Design Datasheet Directory

    EDA Tools

    Verification Functional

  • by AMIQ EDA

    Design and Verification Tools (DVT) is an integrated development environment (IDE) for the e language, SystemVerilog, Verilog, and VHDL. It helps design and verification engineers...

  • by AMIQ EDA

    Thorough audit of your test benches Verissimo SystemVerilog Testbench Linter is a static code analysis tool that allows engineers to perform a thorough audit of their testbenches....

  • Hardware

    Blades

  • by Advantech Co., Ltd.

    Compatible Operating Systems: Red Hat, CentOS, Wind River, 6WINDGate Specification Compliance: PICMG ATCA The MIC-5342 is based on the Intel® platform formerly codenamed...

  • Methods / EDA Tools

  • by ClioSoft Inc.

    ClioSoft ClioSoft’s SOS Design Collaboration Platform is built to handle the complex requirements of system-on-chip design flows. The SOS platform provides a sophisticated multi-site...

  • Design-for-Test (DFT)

  • by Source III, Inc.

    Source III provides the industry’s most comprehensive and cost-effective vector translation product (VTRAN®) which links simulation/ATPG vector data to ATE, a powerful vector...

  • by Source III, Inc.

    With nearly 25 years of field-proven success, VTRAN™ offers the most cost-effective, full-feature solution to creating EDA and ATE test programs from simulation and ATPG vectors....

  • Verification

  • by Agnisys

    IDesignSpec™is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically...

  • by Agnisys

    IDesignSpec™ is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically...

  • by Real Intent

    Meridian CDC is the fastest, highest capacity and most precise clock domain crossing (CDC) solution in the market. It performs comprehensive structural and functional analysis...

  • by Sutherland HDL, Inc

    Founded in 1992, Sutherland HDL has trained thousands of engineers throughout the world on Verilog, SystemVerilog, SVA and UVM. WORKSHOP HIGHLIGHTS Verilog and SystemVerilog...

  • Semiconductor Technologies

    IP - Core

  • by Calypto Design Systems

    Accelerate Time to Rtl, Reduce Verification Effort
    The Catapult® high-level synthesis tool empowers designers to use industry standard ANSI C++ and SystemC to describe functional intent, and move up to a more productive abstraction level.

  • by Calypto Design Systems

    With the explosion of consumer electronics, designing for low-power has become an important design constraint and a key differentiating factor. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, both via automated tools as well as manually by the RTL designers.

  • by Calypto Design Systems

    The emergence of consumer electronics is causing a fundamental shift in Register Transfer Level (RTL) design methodologies. The race for time to market has resulted in the adoption and growth of higher level design creation methodologies. In particular, High Level Synthesis (HLS) directly from software models to hardware has become very popular.

  • by Mixel, Inc.

    Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI® Alliance Specification for M-PHY®....

  • by SmartDV Technologies India Private Limited

    Organizations: EDAC, GSA, EIC, OCP-IP, Si2, SPIRIT SmartDV offers wide range of Verification IP’s, Memory models and Design IP’s. Verification models include complete...

  • by True Circuits Inc.

    Organizations: GSA The TCI DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually,...

  • by True Circuits Inc.

    Organizations: GSA True Circuits’ complete family of standardized, silicon-proven, low-jitter PLL and DLL hard macros spans nearly all performance points and features typically...