Chip Design Resource Center
Top Stories and News
| New White Papers |
Docea Power to present unique solutions for modelling and simulation of dynamic thermal management strategies at DAC
Docea Power, the design for low power company that delivers software solutions for power and thermal analysis at the architectural level , will exhibit at the 50 th Design Automation
From the Blogosphere
Altera introduced a direct memory access (DMA) reference design. The solution is constructed for Stratix V customers needing to seamlessly and quickly design PCIe Gen3 solutions. Stratix V GX FPGAs feature a hardened protocol stack for PCIe Gen3 applications, demanding the highest in bandwidth, system integration and flexibility,...
Cadence Design Systems has issued a call for papers to be presented at MemCon 2013. Cadence is seeking presentations and papers on topics that illustrate users’ knowledge and expertise in memory design and architecture. The deadline for paper abstract submission is May 30, 2013. The MemCon conference showcases the...
Happy Geek Pride Day from the Processors team! We wanted to celebrate this fun holiday with a unique post on Multicore Mix. We asked some of our team members to answer the question, “At what moment in your life did you realize you were a ‘geek’?” Needless to say, they didn’t disappoint!...
DAC 2013 AMS Verification Luncheon: Advance Your Mixed-signal Verification Techniques to the Next Level
Well DAC 2013 is around the corner, so I guess it is time to blog about it, especially since this is in Austin And no, I am not going to tell you about the best BBQ joints or sushi places (yes I did say sushi in Texas) since I lived there for almost 15 [...]...
Designing a glucose monitoring device is made easy with an 8-bit, 8051-based Programmable SoC
Cloud computing will play an increasingly significant role in FPGA designs because the benefits to designers are tremendous. Chip design engineers face a myriad of challenges in
Lattice and Xilinx muse on parallelism, partial reconfigurability, and the state-of-the-art in IP and EDA tools.
Tackling the Challenge of Building Smaller, Lighter, and More Efficient Component-based Avionics with CFD
Computational Fluid Dynamics software helps defense systems designers doubly: it aids in optimizing component SWaP, and models device thermal behavior across time and vendors.
What are the new technologies in the arena?
PCIe is following USB into mobile chip-to-chip applications by adopting the low-power MIPI M-PHY.
IP giant also talks about Intel, finFETs and the cloud Needless to say, ARM Holdings is the dominate supplier of processor intellectual property (IP) in the booming cell-phone
A subtle but important shift is under way inside of EDA. While vendors are still focused on solving some thorny issues at the front end of Moore’s Law, much of the R&D effort
Will the success of the open source movement in software and even hardware cause changes in silicon IP business models?
The shift towards a new class of exascale computers will require new breakthroughs in power management and chip-level technologies like memories, according to a technologist at an event
Organizations: GSA True Circuits’ complete family of standardized, silicon-proven, low-jitter PLL and DLL hard macros spans nearly all performance points and features typically
With the explosion of consumer electronics, designing for low-power has become an important design constraint and a key differentiating factor. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, both via automated tools as well as manually by the RTL designers.
The emergence of consumer electronics is causing a fundamental shift in Register Transfer Level (RTL) design methodologies. The race for time to market has resulted in the adoption and growth of higher level design creation methodologies. In particular, High Level Synthesis (HLS) directly from software models to hardware has become very popular.
Accelerate Time to Rtl, Reduce Verification Effort
The Catapult® high-level synthesis tool empowers designers to use industry standard ANSI C++ and SystemC to describe functional intent, and move up to a more productive abstraction level.