Chip Design Resource Center
Top Stories and News
| New White Papers |
ASSET InterTech and Mentor Graphics announced “seamless interoperability” for the IEEE P1687 Internal JTAG (IJTAG) embedded instrumentation standard. SiliconAid Solutions announced support of IEEE P1687 and IEEE 1149.1-2013 standards through a partnership with Ridgetop Group.
From the Blogosphere
The following is a guest post by Frank Stornello of Verifi. Online fraudsters benefit from the anonymity of a virtual medium. They can invent and reinvent who they are on any given day. And they do. They can change email addresses or IP addresses in just a few clicks. But it’s a little more expensive […]...
I want to learn timekeeping software how to retrieve employee information and time timekeeper I'm starting to connect using TCP / IP and trying to figure out how to send and receive data if anyone has found out about this field, can send a code example desire to help thanks ......
The latest update to Mentor's market-leading PCB design suite aims to unify system definitions across multiple tools to reduce errors....
CDNLive Silicon Valley (March 10-11, 2015, Santa Clara Convention Center) provides an excellent opportunity to share your experiences and insights on key technical and industry issues. And it’s not just about Cadence tools. We’re hosting a track on IP and, if we get enough papers, we'll expand...
The health benefits in our future might just rest on how hale, hardy (and cost-effective) developers, including start-ups, can make their implantable medical device proof-of-concepts—and that warrants a close look at ASSP chips for help with size, power and development time hurdles.
Two 32bit processor IPs have been released by Cortus, the company’s second generation of processor IP that takes a minimalist approach to the ‘third wave’ of applications. Caroline Hayes spoke to Roddy Urqhart, Vice President Sales & Marketing, Cortus.
Embedded designers can follow a roadmap to alleviate graphics challenges when developing for mobile medical, smartphones/tablets, gaming, HDTV and more. With today’s mobile devices
These days, you’d need to be buried under a pile of verification reports not to know that hardware emulation has gone mainstream, moving away from a dusty back room to your cubemate’s
We all know that it’s only a matter of time until our cars are able to communicate with each other. Another wave of connectivity-focused innovation is underway and, this time around,
With anticipated economic limits to the continuation of Moore’s Law now on the horizon, it seems that moving into the 3rd dimension (3D) by stacking multiple layers of integrated
Introduction IEEE 1149.1-2013 is not your father's JTAG. The new release in June of 2013 represents a major leap forward in standardizing how FPGAs, SoCs and 3D-SICs can be debugged
Traditional black box methodologies give way to a novel grey-cell approach for intellectual property (IP) and FPGA clock domain crossing (CDC) analysis. As design complexity escalates,
An on-chip network offers a set of services that allow chip designers and architects to optimize the design to meet the real world requirements of today’s devices, including those
There are many challenges when designing ICs that contain tens to hundreds of millions of gates and it won't get any easier as next-generation designs cross the gigagate threshold.
Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI® Alliance Specification for M-PHY®. The
IDesignSpec™ is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically generate
Founded in 1992, Sutherland HDL has trained thousands of engineers throughout the world on Verilog, SystemVerilog, SVA and UVM. WORKSHOP HIGHLIGHTS Verilog and SystemVerilog
With nearly 25 years of field-proven success, VTRAN™ offers the most cost-effective, full-feature solution to creating EDA and ATE test programs from simulation and ATPG vectors.
IDesignSpec™is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically generate
Meridian CDC is the fastest, highest capacity and most precise clock domain crossing (CDC) solution in the market. It performs comprehensive structural and functional analysis to ensure
Organizations: GSA The TCI DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually,