Chip Design Resource Center

From the Blogosphere

  • Off to Chicago for The Trading Show

    Looking forward to our booth #243 at the Trading Show in Chicago. We’ll have a FastPath Cadence time series analytics unit with us. Should be fun! Viewed 79288 times by 1702 viewers...

  • OSI at OSCON 2015

    Once again the OSI and our Board of Directors will be at OSCON. Just like in years past, the OSI will again be strongly represented with presentations form our Board Directors, Affiliate Members and Individual Members, a booth in the Expo Hall and even a dedicated session on how to use OSI's resources to change the open...

  • Performance and the Use of Port mvl Lists (or, Nothing in Life is Free…)

    When connecting to the DUT signals, we usually refer to the values as 0s or 1s. But sometimes there is a need to know the exact multi-value logic, or to write an mvl value (e.g., init the signal to Z). For this purpose, the e language defines the mvl type – a predefined enumerated type, with values of MVL_U, MVL_X, MVL_0,...

  • No to Know VIP – Part 2

    Continuing on our journey on what is needed to get to productive verification with VIP, the first step is to make the connections between the DUT and the testbench.  This includes connecting the signals, the clock and reset and setting any parameters. This is what we covered in part 1 of the series. Let us […]...

Featured Articles

  • Fuel for the Next Generation of Chip Design

    Q&A with Silicon Cloud CEO Mojy Chian Goliaths, here come the Davids: How IoT is changing a world in which “large semiconductor companies have become larger, and small semiconductor

  • Improved Power Management with Sonics' ICE-Grain

    Compared to conventional, software controlled approaches, Sonics' fine-grain hardware-controlled state transitions enable the architecture to exploit many more "off" and low-power states. It

  • GHz Timing Giving You the Jitters? Three Things You Need to Know

    Clock jitter can adversely affect high-speed protocols such as Ethernet, PCI Express and USB 3.0. You can calm your system down knowing these three simple points. Timing is everything,

  • The Quest for Low Power

    Lowering power consumption requires a holistic approach that touches every aspect of the design, from the transistors to the standard-cell building blocks, to the circuit architecture, and going all the way up to the application software running on the chip and system.

  • DAC Panel: Design Specialists Must Collaborate on Complex SoCs

    A disgruntled designer of analog chips became the focal point of a Design Automation Conference panel session during lunchtime Wednesday.

  • Open-Silicon Wants Your Ideas for ASIC Designs

    Founded in 2003, Open-Silicon has shipped more than 100 million application-specific integrated circuits in its history, according to Vasan Karighattam, the company’s vice president of engineering with responsibility for architecture, system-on-a-chip design and verification, system software, and post-silicon validation.

  • New EDAC Executive Director Looks to Revitalize Organization

    “We need to put more panache around EDA.” That’s Bob Smith, the new executive director of the EDA Consortium, speaking Tuesday afternoon at the Design Automation Conference.

  • Accellera Panel: The Internet of Things Will Depend on Standards

    Standards – the Internet of Things needs them. Most people agree on that. How IoT standards will be developed is up for grabs, according to panelists at a Tuesday morning session at the Design Automation Conference, held by the Accellera Systems Initiative.

Featured Products

  • Industry Leading Tools Linking Simulation and ATPG to Test

    Source III provides the industry’s most comprehensive and cost-effective vector translation product (VTRAN®) which links simulation/ATPG vector data to ATE, a powerful vector analysis

  • Mixel’s MIPI M-PHY

    Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI® Alliance Specification for M-PHY®. The

  • IDesignSpec™

    IDesignSpec™ is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically generate

  • VTRAN Vector Translation Tool

    With nearly 25 years of field-proven success, VTRAN™ offers the most cost-effective, full-feature solution to creating EDA and ATE test programs from simulation and ATPG vectors.

  • IDesignSpec™

    IDesignSpec™is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically generate

  • Expert SystemVerilog and UVM Training Services

    Founded in 1992, Sutherland HDL has trained thousands of engineers throughout the world on Verilog, SystemVerilog, SVA and UVM. WORKSHOP HIGHLIGHTS Verilog and SystemVerilog

  • Meridian CDC

    Meridian CDC is the fastest, highest capacity and most precise clock domain crossing (CDC) solution in the market. It performs comprehensive structural and functional analysis to ensure

Chip Design Datasheet Directory

    EDA Tools

    Verification Functional

  • by AMIQ EDA

    Design and Verification Tools (DVT) is an integrated development environment (IDE) for the e language, SystemVerilog, Verilog, and VHDL. It helps design and verification engineers...

  • by AMIQ EDA

    Thorough audit of your test benches Verissimo SystemVerilog Testbench Linter is a static code analysis tool that allows engineers to perform a thorough audit of their testbenches....

  • Methods / EDA Tools

    Design-for-Test (DFT)

  • by Source III, Inc.

    Source III provides the industry’s most comprehensive and cost-effective vector translation product (VTRAN®) which links simulation/ATPG vector data to ATE, a powerful vector...

  • by Source III, Inc.

    With nearly 25 years of field-proven success, VTRAN™ offers the most cost-effective, full-feature solution to creating EDA and ATE test programs from simulation and ATPG vectors....

  • Verification

  • by Agnisys

    IDesignSpec™is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically...

  • by Agnisys

    IDesignSpec™ is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically...

  • by Real Intent

    Meridian CDC is the fastest, highest capacity and most precise clock domain crossing (CDC) solution in the market. It performs comprehensive structural and functional analysis...

  • by Sutherland HDL, Inc

    Founded in 1992, Sutherland HDL has trained thousands of engineers throughout the world on Verilog, SystemVerilog, SVA and UVM. WORKSHOP HIGHLIGHTS Verilog and SystemVerilog...

  • Semiconductor Technologies

    IP - Core

  • by Calypto Design Systems

    Accelerate Time to Rtl, Reduce Verification Effort
    The Catapult® high-level synthesis tool empowers designers to use industry standard ANSI C++ and SystemC to describe functional intent, and move up to a more productive abstraction level.

  • by Calypto Design Systems

    With the explosion of consumer electronics, designing for low-power has become an important design constraint and a key differentiating factor. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, both via automated tools as well as manually by the RTL designers.

  • by Calypto Design Systems

    The emergence of consumer electronics is causing a fundamental shift in Register Transfer Level (RTL) design methodologies. The race for time to market has resulted in the adoption and growth of higher level design creation methodologies. In particular, High Level Synthesis (HLS) directly from software models to hardware has become very popular.

  • by Mixel, Inc.

    Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI® Alliance Specification for M-PHY®....

  • by SmartDV Technologies India Private Limited

    Organizations: EDAC, GSA, EIC, OCP-IP, Si2, SPIRIT SmartDV offers wide range of Verification IP’s, Memory models and Design IP’s. Verification models include complete...

  • by True Circuits Inc.

    Organizations: GSA The TCI DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually,...

  • by True Circuits Inc.

    Organizations: GSA True Circuits’ complete family of standardized, silicon-proven, low-jitter PLL and DLL hard macros spans nearly all performance points and features typically...