Table 1. Comparison between ZeBu, best-in-class emulation systems and FPGA-based prototypes

Unprecedented device complexity and embedded software content are driving the need for a new hardwareassisted verification approach. EVE’s ZeBu is a breakthrough architecture that combines the strengths of traditional emulation and rapid prototyping into a unified platform for both hardware and embedded software development. For the first time a single platform and design representation can satisfy the needs of both these applications, enabling hardware designers and software developers to communicate and collaborate in a way that was never possible before. The net benefit of ZeBu’s unifying approach is to accelerate hardware/ software integration well ahead of first silicon, reduce unnecessary respins and software revisions, and shorten time to market.

As shown in Table 1, ZeBu is much faster and more affordable than bestin- class emulation systems. ZeBu also is much easier to use, offers much higher capacity and better hardware debugging than FPGA prototyping systems. In addition, ZeBu’s integration with popular HDL simulators and with high-level of abstraction testbenches at transaction-level provides the highest performance level in the industry, reducing coemulation overhead by at least one order of magnitude.

Figure 1. ZeBu’s patented Reconfigurable Testbench (RTB) architecture enables efficient co-emulation with PC-based simulators, or C, C++, SystemC, SystemVerilog models written at high-level of abstraction and provides extensive visibility to the emulation resources

ZeBu has been architected to meet the needs of both hardware and embedded software engineers, and to provide them with the hardware and software debugging capabilities required for debugging complex embedded SoC designs.The ZeBu compiler automatically handles any design, regardless of size, coding style, clocking scheme, or memory structure, making it easy to map even large designs. Historically, these have been the biggest problems with other FPGA-based rapid prototyping systems.

ZeBu’s patented Reconfigurable Testbench (RTB) architecture makes the system especially well suited for hardware debugging applications. The RTB controls and optimizes how the emulated system receives stimulus and communicates with software running on the workstation. Based on a powerful C/C++ API, the RTB communicates directly with HDL testbenches (VHDL, Verilog, SystemVerilog) and with abstract system level models (C, C++, SystemC™ or SystemVerilog™). The RTB supports communications both at the signal/bit-level and at the transaction-level. The latter is an especially efficient sustaining an industry leading data transfer rate in excess of up to 1Gbit/sec between ZeBu and the software testbench with very small latency. The RTB is used to implement complex synthesizable transactors, synthesizable testbenches, or even synthesizable assertions.

Table 2. Six modes of operation supported by ZeBu

Figure 2: Example of virtual platform based on a set of transactors used to verify a popular PDA core

The RTB also provides all the controllability and observability functions required by hardware designers in order to debug their design. For example, the RTB supports interactive read/write access to all design-under-test registers and memories at run-time, without needing to compile internal probes.

ZeBu Operating Modes

ZeBu supports six operating modes (see Table 2) that help exploit Zebu’s performance throughout the design cycle.

All of the above modes can be combined to create a complex test Operating Mode Description Co-emulation with commercial HDL simulator A co-emulation link connects ZeBu to any VHDL, Verilog, SystemVerilog simulator, such as VCS™, NC-Sim™ or ModelSim™. Co-emulation with C, C++, SystemC, SystemVerilog at Signal-level Via a C/C++ API a design-under-test mapped onto ZeBu can be connected to C, C++, SystemC, SystemVerilog testbenches at the cycle level. Co-emulation with C, C++, SystemC, SystemVerilog at Transaction-Level When the design-under-test includes bus interfaces (such as Ethernet, PCIe, USB, Sonet…), it is possible to drive it with C, C++, SystemC, SystemVerilog testbenches at the transaction level at MHz speed. Test Vectors In test-vector mode, a pattern file is captured during HDL or C/C++ co-emulation that can be played back at higher speed without the HDL simulator or the C/C++ testbench present. The pattern execution tool detects output signals. This mode accelerates regression testing of designs before tape-out. Emulation with Synthesizable Testbench A synthesizable testbench can be embedded in the RTB to enable emulation at several MHz. This mode provides the best level of performance since there is no interaction with any external software or hardware components. In-Circuit Emulation with Target System In this mode, the emulated design-under-test is wired to a target system, which behaves as a physical testbench. A built-in logic analyzer running at up to 20MHz can trace the design states over long emulation runs. Complex triggers can be added to control the tracing mechanism Table 2. Six modes of operation supported by ZeBu Table 2. Six modes of operation supported by ZeBu environment. For example, a test environment could include a synthesizable testbench mapped in the RTB, an application program embedded in a DRAM synthesizable model, a set of protocol transactors (USB, Ethernet, Audio, etc.) driven by C++ models executed on the host PC/Linux, a JTAG transactor connected to a S/W debugger running on a PC/Windows and an LCD transactor displaying an LCD image stream directly on the host PC.

ZeBu Applications

ZeBu’s flexibility enables its use throughout the hardware and embedded software development cycle to:

• Verify and debug ASICs/SoCs, IP cores




• Co-verify the integration of hardware with embedded software (OS and firmware)




• Develop and debug embedded software

These applications are detailed below:

• Verify and debug ASICs/SoCs, IP cores With its integrated hardware debugging resources and high execution speed, ZeBu is ideal for verifying and debugging complex hardware blocks, IP cores and full chip designs. Early in the design cycle Zebu can be used as a simulation accelerator in co-emulation with leading HDL simulators and/or C/C++ code. ZeBu can be driven by existing HDL testbenches with no modification. Later in the design cycle, a virtual platform made up by high-level testbenches can drive the DUT via a set of transactors. See Figure 2. ZeBu has been architected for especially fast coemulation at the transaction level, with operating speeds of up to 30MHz.




• Co-verify hardware and software integration ZeBu can execute software drivers and operating systems at MHz speed, while supporting full hardware and software debugging capabilities. For software debugging, the system’s processor can be connected through a JTAG cable or a JTAG transactor interface to standard embedded software debuggers from ARM, TI, ARC, etc. Via a JTAG transactor-based connection the engineer can stop the clock and easily trace HW bugs in the design hardware. This enables hardware and software development teams to work on the same design representation and to collaborate on the resolution of integration issues in a way that was never possible before.




• Develop and debug embedded software with reduced-cost “replicates” ZeBu can be used as a software validation platform for embedded software developers. The embedded software can be downloaded into the design memory via the PCIe interface in a fraction of second, much faster than via the JTAG port. Also, ZeBu’s save and restore capability can be used to skip the OS boot phase and advance directly to the point in the code at which a problem was detected. Since hardware debugging features are not required at this stage, EVE offers a “replicate” version of ZeBu that is optimized for the needs of embedded software developers at a fraction of the cost of a full ZeBu system. In this way, the user can leverage the same system model used for hardware verification while controlling overall costs. The net result is that ZeBu users are better able to parallelize hardware and software validation tasks, and accelerate the time to market significantly.

Summary With a highly cost-effective architecture, ZeBu makes emulation more accessible than ever before: accessible to both SoC designers and embedded software developers, accessible throughout the design cycle, and accessible by groups with modest EDA budgets. Overall, ZeBu clearly provides the best return on investment of any hardware-assisted verification approach.