ZeBu-Personal is built on an extended PCI Express mother-board that fits a daughter card mounted with three Virtex5-LX330 FPGAs and a set of 512Mbit SSRAM and 2Gbit DDR2 DRAM chips. A network of fast LVDS differential pairs interconnects all FPGAs and memory chips, including the I/O interfaces. Two of the three LX330 FPGAs map the Design-Under-Test (DUT) while the third LX330 FPGA implements the patented Reconfigurable Test Bench (RTB) that interfaces the DUT to the test environment. Via a proprietary C/C++API, the RTB controls and optimizes the communication between the emulated design and the VHDL/Verilog/SystemVerilog testbench or C/C++ or SystemC™ models running on the workstation. The RTB supports communications at signal/bit- level and at transaction-level. The latter is especially efficient, sustaining an industry leading data transfer rate of 1Gbit/sec with a latency of 2 microseconds (500M messages/sec ).

The RTB is used to implement tens of synthesizable transactors, synthesizable testbenches, or even synthesizable assertions. Further, the RTB provides interactive read/write access to all internal registers and memories at run-time, without needing to compile internal probes.

An in-circuit emulation interface connects ZeBu-Personal to a target system and/or to hard IP cores via a maximum of 360 single-ended I/O pins, plus 24 LVDS pairs. In addition, ZeBu-Personal interfaces with popular embedded software debuggers via a physical JTAG connection based on a 32-pin interface, called SmartICE, or via a virtual JTAG transactor for added flexibility and remote usage.

FEATURES & BENEFITS

• Completely automated compiler from RTL, including: memory generation, automatic clock-tree mapping to remove timing violations due to gated-clocks, muxed-clocks and divided clocks
• Comprehensive hardware debugging environment, including full visibility of internal signals, VCD & FSDB waveform generation, HW triggers, support for synthesizable assertions
• Software debugging interfaces to popular embedded software debuggers for ARM, PowerPC, ARC, Tensilica, TI DSP, and other CPU/DSP cores

TECHNICAL SPECS

• Max Capacity: 5M ASIC gates mapped on two V5- LX330 FPGAs
• On-board RAM for Design: Up to 30Mbit BRAM, 512Mbit SSRAM (16 ports) and 2Gbit (4 ports) DDR2 DRAM.
• On-board RAM for at-speed Tracing: 2Gbit DDR2 DRAM
• Design Clocks: 16 independent primary clocks and unlimited number of derived clocks
• On-board RAM for at-speed Tracing: 2Gbit DDR2 DRAM
• In-Circuit Interface: 360 single-ended I/O pins and 24 LVDS pairs plus 8 external clocks
• In-Circuit Interface: 360 single-ended I/O pins and 24 LVDS pairs plus 8 external clocks
• Form Factor: PCIe card, 8x lanes

INDUSTRIES SERVED

Graphics & multimedia, networking, processors, consumer, storage.