Cobalt Timing Constraint Generation eliminates the manual, iterative and error-prone task of identifying and writing timing constraints for false and multi-cycle paths in complex designs. Cobalt reads and operates directly on your RTL to automatically generate a comprehensive and accurate set of timing exceptions, allowing you to achieve significant reductions in design cycle times for both ASIC and FPGA design flows. Automatically generating timing exception constraints reduces the burden on synthesis and place & route tools, resulting in fewer iterations and enhanced quality of results (QoR). In addition to increasing design productivity, Cobalt significantly reduces the risks associated with manual generation of timing constraints.

Cobalt’s automatically generated assertions can be used with third party tools to verify the timing constraints and increase design confidence.

FEATURES & BENEFITS

• Automatically identifies false and multi-cycle paths
• Supports industry standards for easy integration into digital design flows
• Generates constraint files in SDC format.
• Generates assertions in standard formats such as PSL and SVA