As designers migrate to process sizes of 0.25um and smaller, interconnect coupling becomes much more important. This effect is intensified because circuits are operating at higher frequencies and lower voltages. As process size becomes smaller, interconnect thickness increases to offset the increase in resistance due to the interconnect width getting smaller. This makes the effects of lateral coupling capacitance much more significant than vertical coupling capacitance. Lateral coupling can lead to different timing behavior and including it in simulations is required to accurately calculate delay and circuit behavior.

Designers need the ability to accurately and quickly extract circuit parasitics so they can get the design right the first time. HiPer PX is a high performance parasitic extraction tool that is integrated with Tanner’s L-Edit layout editor for easy and rapid extraction of parasitics. It can quickly extract simulation-ready SPICE netlists from the layout, including devices (MOSFETs, bipolars, etc) and interconnect parasitics, including vertical and lateral coupling capacitance. HiPer PX has two distinct modes of operation: fast 2D and accurate 3D modes.

FEATURES & BENEFITS

• Fast 2D Extraction
  HiPer PX 2D is an extremely fast, flat or hierarchical extraction engine. It is based on an efficient finite-element method to accurately extract interconnect resistances and a fast and comprehensive interpolation method to extract vertical and lateral coupling capacitance.
• Accurate 3D Modeling
  HiPer PX 3D efficiently models the entire circuit, and performs a physics-based extraction based on physical parameters (thickness, edge geometry, dielectrics, and resistivity). It uses an enhanced finite-element method with mesh optimization to accurately extract interconnect resistances, and a robust boundary-element method for capacitance extraction.
• Performance and Accuracy
  HiPer PX can run incrementally, so only cells that have changed need be re-extracted. In addition, the extract can be performed using different settings at different hierarchy levels—so smaller leaf cells could be extracted in 3D mode, while interconnects between them can be extracted in the faster 2D mode. Both methods have a time complexity that is linear to the size of the layout and a sub-linear memory usage. HiPer PX is fast and scalable, and can easily handle 10,000 fully flattened transistors in 3D mode, and 1,000,000+ transistors in 2D mode.
• Netlist Reduction
  HiPer PX generates compact and accurate RC models for interconnects that include higher-order moments and that are guaranteed to be accurate up to a userdefined signal frequency. HiPer PX uses an advanced algorithm to break interconnect nodes into RC components, maximizing simulation accuracy while reducing netlist size and simulation time.
• When you purchase a new design tool, licensing options can greatly affect your total cost of ownership. HiPer PX is available in node-locked and networked configurations offering you the most flexible licensing possible. With a single solution, HiPer PX will work whenever and wherever meeting the design needs of your main workgroup and remote workers. If you offshore design projects, HiPer PX does not have geographic restriction on its licenses, thus, lowering your total cost of ownership.

INDUSTRIES SERVED

Audio, Automotive, Consumer Products, Defense, Industrial, Telecommunications, Wireless