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HiPer Verify™ is a comprehensive yet affordable solution for analog/mixed-signal IC design rule checking (DRC) and hierarchical netlist extraction on the PC-platform.
Most foundries provide DRC and LVS rules in Calibre® or Dracula® format. When you change your process or feature size, you must update your DRC & LVS rules—a time-consuming process. HiPer Verify uses advanced hierarchical algorithmic techniques to provide optimal performance for your designs.
HiPer Verify can run Calibre and Dracula rule files directly from the foundry. When your verification process changes, you can simply reference the new DRC or LVS command file from the foundry, meeting your existing standards right out of the box. You get the security of knowing you are running your rule files without modification or conversion, and the convenience of not having to perform translations.
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FEATURES & BENEFITS
- Easily maintain foundry compatibility
• Execute multiple DRC command files sequentially in a single DRC run.
• Run batch DRC or netlist extraction on multiple cells.
• Process results from a DRC check in subsequent DRC operations for powerfully complex checks, which is especially useful for 130nm and below.
• Verify your most complex analog or mixed-signal designs through support for orthogonal, 45°, allangle, and curved layouts.
• Perform electrical rule checks (ERC) in addition to design rule checks (DRC), through support for connectivity- based DRC rules including antenna checks.
• Extract a hierarchical SPICE netlist from layout using a Calibre or Dracula format LVS command file.
• Perform default property computations for built-in devices or create user code to compute custom properties from a set of pin and auxiliary layers.
- Increase productivity with hierarchical DRC and netlist extraction HiPer Verify’s verification engine is designed to take advantage of the hierarchy and repetition in today’s IC designs. HiPer Verify’s hierarchical rule checking engine finds violations in the cell where they occur. This enables you to correct a violation once rather than sorting through many duplicate violations as flat processing requires.
• HiPer Verify’s hierarchical extraction engine generates a hierarchical netlist for easier LVS.
• Run DRC in the background so you can continue layout or fix DRC violations while DRC is still running.
- Find and fix violations quickly
• View violations in either the top cell or the cell where the violation occurred.
• Mark violations as they are fixed so you can save your progress.
• Import DRC results from a Calibre DRC results file for viewing in L-Edit.
- Edit DRC and LVS command files easily
Composing and debugging command files requires specialized knowledge of command language syntax. HiPer Verify includes a syntax (keyword) highlighting text editor specifically designed for speeding up the job of editing DRC and LVS command files.
- Reduce verification costs
Increase your number of verification licenses without increasing your overall tool costs. With its native compatibility, you can integrate HiPer Verify into your existing tool flow with little effort. By purchasing fewer expensive tool licenses and using them only for final verification, you will save money and reduce your maintenance costs.
INDUSTRIES SERVED
Audio, Automotive, Computer Services, Consumer Products, Defense, Industrial, Security, Telecommunications, Wireless
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