Challenges At 32nm And Beyond
Contact Information
Mentor Graphics
739 N. University BlvdMobile, AL, 36608
USA
tele: 251.208.3400
fax: 251.343.7074
embedded_info@mentor.com
www.mentor.com/embedded
print
Mobile, AL, 36608
USA
tele: 251.208.3400
fax: 251.343.7074
embedded_info@mentor.com
www.mentor.com/embedded
Mobile, AL, 36608
USA
tele: 251.208.3400
fax: 251.343.7074
embedded_info@mentor.com
www.mentor.com/embedded
Comments
Leave a Reply
Featured White Papers
Evolving the Coverage-driven Verification Flow
Verification methodology has undergone dramatic changes over the past decade. The realization that larger and more-complex designs required more and more verification effort, coupled with shrinking schedules, spawned new languages specifically tailored for verification and tools intended to make the verification process more predictable and efficient.
Power Consumption at 40 and 45 nm
At 40 and 45 nm process nodes, power has become the primary factor for FPGA selection.
Accurately Analyzing Power in a Simulink Software Model-Based Design Flow
Frequency, run time, and area utilizations are widely used as benchmarking metrics to gauge quality of results (QoR) for FPGA designs and tool performance.
Capabilities to Maximize Productivity for FPGA Debug and Verification
Whether your task is to verify the functional correctness of a design, ensure adequate timing performance, or to quickly bring up a hardware platform in the lab environment, efficient verification and debug typically requires evaluating the design from multiple perspectives—ranging from high-level functional characteristics to low-level performance details—each at different phases of the design flow.
Synopsys White Paper: Understanding the real cost of prototyping hardware
This white paper provides an in depth look at significant factors to consider when choosing to develop or purchase prototyping hardware. Costs, development time, and effort are considered in detail as well as other factors such as Bill-of-materials cost, manufacturing time, and test yield. The paper also provides information on how to request a “Cost Comparison Spreadsheet” which will allow you to explore the various options and make an informed decision for your particular situation.
The PSP Model in RF CMOS Design
This white paper explains the technology behind Penn State Philips (PSP) transistor models and how they relate to actual device behavior.
Diamond Sponsor
Gold Sponsors
Affiliate Sponsors
Got a Question?
Grappling with difficult embedded electronics or software/IT issues? Tap into our community of experts and get real answers.
Click here to Ask The Experts
EE Catalog Tech Videos
Value Shifts In The Semiconductor Supply Chain
System-Level Design discusses where the money has shifted in the semiconductor supply chain with Synopsys, eSilicon, TSMC and Avago.
Challenges At 32nm And Beyond
Wally Rhines, chairman and CEO of Mentor Graphics, talks about what’s changing in design, the effect of low power, and who’s going to be doing the most advanced designs.
Tesla: The Ultimate Low-Power Design
When your battery pack alone costs $30,000 and you get 200 miles per charge, you’ve got to be looking for ways to save power. The Tesla roadster is crammed with parts from many Silicon Valley companies, all designed to draw as little power as possible. But there’s still much more work to be done.
Artificial Intelligence: This Time It’s For Real
AI used to be the stuff of science fiction, but cheap processing power and storage has made it a reality. To find out what’s being developed, System-Level Design (www.chipdesignmag.com/sld) tracked down Rachel Goshorn, assistant professor of System Engineering at the Graduate School of Engineering and Applied Science in the Naval Postgraduate School in Monterey, Calif. Check out what she has to say.
New Memory Technology Ahead
Christophe Chevallier, vice president of engineering at Unity Semiconductor, sat down with System-Level Design Contributing Editor Pallab Chatterjee to talk about multilayer technology that could boost chips to more than a terabyte using standard CMOS processes.
Saving Power By The Milliwatt
Power budgets may look small, but the amount of power that can be saved with different design approaches will surprise you.
What Goes Wrong
The best way to figure out where the problems are with products is to check with customer service. They hear everything. So System-Level Design sat down with Tom Flodeen, VP of customer service at Mentor Graphics to see where customers are asking questions. Yeah, we know there’s a little marketing in this, but it’s worth wading through to listen to what’s going on behind the scenes.
Calendar of Events
First Annual Workshop on Micro Power Technologies
Radisson Hotel, San Jose, CA October 22, 2009 http://www.micropowertech2009.com/
DesignCon2010
Santa Clara Convention Center, CA February 1-4, 2010 http://www.designcon.com/2010/
Multicore Expo
San Jose, CA April 26-29, 2010 http://www.multicore-expo.com/
DAC
Anaheim, CA June 13-18, 2010 http://www.dac.com/47th/index.aspx
Microelectronics Packaging & Test Engineering Council
MEPTEC Presents a One-day Symposium From Chip to System: Design Challenges and Solutions Holiday Inn, San Jose, CA February 25, 2010 http://www.meptec.org/meptecfromchipto.html