HiPer Verify™ is a comprehensive yet affordable solution for analog/mixed-signal IC design rule checking (DRC) and hierarchical netlist extraction on the Windows® and Linux® platforms. HiPer Verify’s verification engine is designed to take advantage of the hierarchy and repetition in today’s IC designs. HiPer Verify’s hierarchical rule checking engine finds violations in the cell where they occur. This enables you to correct a violation once rather than sorting through many duplicate violations as flat processing requires.

Most foundries provide DRC and LVS rules in Calibre®, Assura®, or Dracula® format. When you change your process or feature size, you must update your DRC and LVS rules—a time consuming process. With HiPer Verify, you can simply reference the new DRC or LVS command file from the foundry, meeting your existing standards right out of the box. You get the security of knowing you are running your rule files without modification or conversion, and the convenience of not having to perform translations.

Increase your number of verification licenses without increasing your overall tool costs. With its native compatibility, you can integrate HiPer Verify into your existing tool flow with little effort. By limiting expensive tool licenses to only final verification, you will save money and reduce your maintenance costs.

FEATURES & BENEFITS

• Increase productivity with hierarchical DRC
• Run Calibre, Assura and Dracula DRC and LVS rule files directly from the foundry.
• Verify your most complex analog or mixed-signal designs through support for orthogonal, 45°, all-angle, and curved layouts.
• Process results from a DRC check in subsequent DRC operations for powerfully complex checks, which are needed for 130nm and below.
• Perform electrical rule checks (ERC) through support for connectivity based DRC rules including antenna checks.
• Run DRC in the background so you can continue layout or fix DRC violations while DRC is still running.

• Extract a hierarchical SPICE netlist from layout using a Calibre or Dracula format LVS command file.
• Perform default property computations for built-in devices or create user code to compute custom properties from a set of pin and auxiliary layers.
• Run batch DRC or netlist extraction on multiple cells.

• View violations in either the top cell or the cell where the violation occurred.
• Mark violations as they are fixed so you can save your progress.
• Import DRC results from a Calibre DRC results file for viewing in L-Edit.
• Zip through LVS with cross-probing from SPICE netlists and LVS results to layout or schematic and with enhanced navigation of SPICE netlists.
• Easily highlight shorts and opens.

System Requirements

• Microsoft® Windows XP, Windows Vista™ or Red Hat Enterprise Linux Version 4 or 5
• Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
• 1280 x 1024 Resolution—True Color (24-bit)
• 3 button mouse

INDUSTRIES SERVED

Audio, Automotive, Biometric, Consumer Products, Defense, Industrial, Healthcare, Telecommunications, Wireless

Contact Information

Tanner EDA

825 S. Myrtle Avenue
Monrovia, CA, 91016
USA

tele: +1.626.471.9700
toll-free: 877.325.2223
fax: +1.626.471.9800
sales@tanner.com
www.tannereda.com