The verification industry is rife with new validation technology. Each technology leads to ever-more abstraction, compartmentalization, and productivity enhancements. Within the past few years, two major verification methodologies have been released to enable SystemVerilog (SV) testbench-based verification: the VMM methodology developed by ARM and Synopsys and the OVM methodology—a joint effort by Cadence and Mentor Graphics. Many lesser-known and often in-house methodologies also are being used, which leads to an ample and growing set of legacy VIP code written under specific methodologies.

For any number of reasons, companies are looking seriously at being able to take existing VIP from one methodology and use it with VIP from other methodologies. Typically, legacy code exists in one methodology and companies want to convert to the other methodology. Alternatively, they may wish to consume existing external VIP from a third party. In both cases, their methodology experts are called on to integrate the two VIPs to make them work together. Sometimes the integration is straightforward like attaching a monitor. Most often, however, the work is extensive and requires expert knowledge about both methodologies to make them interoperate correctly.

To provide adequate solutions for this growing problem, an Accellera TSC consisting of 14 major companies was formed in May of 2008. Its goal is to understand the issue in depth and—ultimately—provide two solutions. The short-term objective is to deliver a solution for VIP interoperability as a ‘Recommend Practice’ document. The long-term solution is to be a common base class library (BCL) in the form of a ‘standard’ specification.

This task was monumental in bringing the EDA industry together with the goal of bridging communication across existing VIP—not only for the OVM and VMM, but extending to other languages and methodologies like SystemC and ‘e.’ We noted many of the interoperability challenges of the verification community:

• Instantiating and building different VIP components within the testbench
• Coordinating different VIP simulation phases and scheduling
• Configuring VIP components for the desired operation mode from the other VIP
• Orchestrating and coordinating stimulus and other traffic between different VIP components
• Passing data types between different VIP components
• Distributing notifications across all VIP components
• Issuing and controlling messages using the different VIP messaging mechanisms

A year later, the outcome of the TSC isn’t just a recommended practice document on VIP interoperability. A potential ‘standard’ specification on interoperability exists, given the fact that an application programming interface (API) was also developed along with a reference interoperability library. Although it only targets VMM/OVM interoperability, the specification is still very much applicable to other methodologies and languages. The amount of cooperation amongst TSC members was astounding, with all of the participants significantly contributing to the end goal.

The “Recommended Practice” document isn’t biased toward either VMM or OVM. In fact, it provides details to the end user on how to work with either verification environment on top. As can be seen in the Figure from the recommended practice document, the solutions provided can be consumed by VMM-centric or OVM-centric users needing to pull in foreign VIP.

Figure: This graphic shows both VMM-on-top and OVM-on-top examples.

In the recommended practice document, an entire chapter is devoted to introducing the high-level concepts of interoperability and component integration. The chapter outlines a process that can be used by the verification environment writer to determine which cross-referenced best-practice sub-chapter(s) applies to his or her specific integration challenge.

The main chapter of the interoperability document contains 12 sub-chapters dealing with the following topics:

• OVM-on-top and VMM-on-top phase synchronization
• VIP configuration
• Meta-composition
• Data conversion
• TLM-to-channel and channel-to-TLM communication
• Analysis to channel and channel to analysis
• Notify to analysis and analysis to notify
• Callback adapter
• Messaging

Each subject stands on its own, thereby enabling the verification-environment owner to walk through a specific interoperability issue and follow its recommended solution. Every sub-chapter details the intent of the practice and the motivation behind it. It then provides examples, reference adapters, and wrappers to use along with diagrams that show topological hookup. Lastly, it describes the implementation. The interoperability document describes a broad range of interoperability from a simple monitor hookup to integrating a complex sequence generator. In addition, the reference library provides an interoperability class library with the adapters and wrappers needed to hook up the components from the VMM to the OVM and vice versa.

This summer, the VIP TSC is due to submit the recommended practice document to the Accellera board for approval. At that point in time, we’ll begin working on our long-term commitment of a common base class library.

Overall, it’s been an incredible journey for all of us on this TSC. No one could have guessed that we would have accomplished so much in such a short amount of time. The document and the reference library will have a profound impact on the verification industry. They will allow greater interoperability and VIP reuse between the VMM and OVM. By permitting extensions to other languages, they also will give the industry a source for multi-language verification interoperability.

In the long run, we’ll work toward a common BCL to which the industry can move. In the process, we’ll avoid the overhead of interoperability between SV-based verification methodologies. We expect to leverage the interoperability implementation that’s already provided as a permanent solution to other languages and as an intermediate solution to SV-based methodologies until they’re fully converted to the common BCL.

Thomas Alsop of Intel Corp. is co-chair of the VIP TSC. Alsop graduated with a bachelors of science from BYU in 1996 in electrical and computer engineering. He spent his first 10 years at Intel as a design engineer on five major CPU design teams including the Pentium4, Core 2 Duo, and Core i7. Alsop has spent the last 2+ years with the Corporate Design Solutions team as a methodology, tool, and flow expert, providing training and packaged RTL design and validation environments and solutions for design teams across Intel.