The cost of design is starting to come down with top quality and faster results.

The world has changed dramatically in the last 12 months, causing design teams to change their thinking. Many companies are now investing heavily to guarantee not only their survival but also their leadership positions when the global economy recovers. One area of investment is SystemC, electronic system level (ESL), and high-level synthesis (HLS)—sometimes referred to as behavioral or algorithmic synthesis. Design teams are turning to these emerging methodologies to save money while improving their overall design and verification productivity. Newer technologies promise to completely replace existing register-transfer-level (RTL) design methodologies while leveraging investments in RTL design and verification tools as well as legacy RTL intellectual property (IP).

Conventional wisdom has contended that HLS offers significant improvements in productivity, but quality of results (QoR) suffers. This is simply not the case. Leading HLS products—especially those based on SystemC—often produce results that significantly beat hand-coded RTL implementations for both datapath and control-based designs. These tools utilize advanced compiler techniques, which are similar to the C/C++ compiler, to optimize the design’s microarchitecture for the best performance, area, and even power.

Figure 1: This mobile-video codec was re-implemented using SystemC and HLS after having been completed in RTL code.

The trend—especially in consumer electronics—is to move toward smaller and more portable designs. With time to market, performance, cost, and power all being key concerns, design teams must find innovative ways to manage all of these parameters. More importantly, they must be able to make tradeoffs between them. Consider a recent design completed with a leading high-level synthesis product (see Figure 1). This design is part of a codec for mobile video that was re-implemented using SystemC and HLS after having been completed in RTL code. While this design block is relatively small, the results scale for larger blocks as well.

As the data shows, this project reaped significant benefits by using the HLS process. The time-to-RTL went from 12 to 2 weeks, representing an 83% decrease in the time required to get to a viable RTL implementation. In addition, the design area decreased by 45%, thanks to the HLS tools’ optimizing compiler. During the various phases of high-level synthesis, the tool optimized the type of functional units and storage being used including adders, multipliers, and registers. It also minimized the number of functional units and storage. Quite often, an HLS tool can find opportunities to optimize the area, which won’t be readily apparent to the hardware designer implementing the design with hand-coded RTL. This is due to the compiler’s ability to handle much greater degrees of complexity in terms of states in the finite state machine (FSM) or operator counts, for example.

It also is worth noting that the power of this design was reduced by 59%. Much of this power savings came from the reduction in area though the HLS tool. In this case, it automatically implemented known best-practice coding styles wherever possible, such as operand isolation—a well-known power-reduction technique. This approach created more effective RTL code while optimizing the code for the downstream logic synthesis, power optimization, and place-and-route tools. Although it isn’t indicated in Figure 1, the measured performance was the same between the RTL code and the HLS design. The HLS block was replacing an existing RTL block. The functional timing or latency was therefore fixed.

Doing More With Less
Improving productivity is at the heart of the value pitch for every electronic-design-automation (EDA) tool and an important consideration in today’s economic climate. HLS promises to cut design creation time significantly––in this case, above ~7X. That number can be higher, depending on the expertise of the user. As one digs further into the data, it’s interesting to note that the productivity benefit isn’t limited to “time-to-RTL.” It also significantly affects verification. The higher level of abstraction allowed for fewer lines of code to represent the design intent. The result was fewer bugs, faster simulations (~10X to 100X RTL code), and much earlier access to the verification platform.

Figure 2: This graphic illustrates the productivity benefits of HLS versus RTL coding.

Recently, Figure 2 was presented at a users’ group meeting in Japan by a designer who was implementing a mobile audio platform. It illustrates the productivity benefits of HLS versus RTL coding. The majority of design blocks took about 67% less time than RTL coding. One block took 50% less time, although it was implemented by a SystemC/HLS beginner.

Impact On QoR
Quality of results (QoR) is critical to the bottom line—whether it’s optimizing the design to make it sufficiently fast and low in power to be competitive in the market or reducing area to lower silicon costs, thereby squeezing out an extra percentage of margin. But simply looking at area, power, and speed isn’t enough. Design teams need to dig into these attributes to see what derivative benefits lie within.

The performance of the design is critical to meeting market needs. If it took 10 min. to save a 2-megapixel image to memory, that new digital still camera wouldn’t be very functional. To that end, design teams must be able to constrain the HLS tool to meet strict performance requirements—most often latency and throughput—for their designs. The HLS tool, in turn, should properly allocate functional resources to meet demanding schedules while minimizing overall area. All tools should be able to perform these tasks without any sacrifice from hand-coded RTL.

Of course, opportunities exist for improving RTL code in the area of performance. Quite often, the HLS tool can find a much more optimal schedule that results in better performance and may also include an area improvement, depending on the situation. To manage complexity, designers may have to make tradeoffs or design decisions that ultimately result in a design with inferior results. Examples of such tradeoffs are limiting FSM complexity, adding more resources, or using more expensive resources like multiport memories. The modern HLS tool can manage complexity while finding the optimal schedule to meet performance goals.

Silicon Area
The design’s silicon area directly impacts its cost as well as other quality metrics. To keep costs down, designers must spend a great deal of time optimizing a design to reduce area. As shown in Figure 1, leading HLS tools can provide a significant reduction in area while reducing the time that it takes to create the RTL code. However, the benefits reach further into the design process. For instance, well-designed RTL code can dramatically improve the RTL logic synthesis flow. Optimized designs will be easier to route, have few if any timing closure problems, and require less iteration in RTL synthesis—potentially eliminating days or weeks of work.

Verification
HLS also benefits the verification process by providing a high-speed, accurate, implementable model far earlier in the process than RTL code. By having this model available, the design team can jump right into initial functional testing using the code or design from which the implementation will be automatically derived. In addition, the design team can utilize the HLS tool’s ability to retarget from an application-specific integrated circuit (ASIC) to a field-programmable gate array (FPGA) to create a prototype or run in an emulation environment for early software integration.

One critical component to verification with HLS is the ability to utilize a single testbench throughout the design flow. This aspect improves productivity while minimizing the risk of errors. Tools that utilize SystemC inherently have the ability to model an accurate input/output interface and simulate that interface together with the design functionality in a single language. High-speed ANSI-C-based tools, on the other hand, don’t adequately allow the design team to fully model the complete design and verify it at the high level. The resulting RTL code must be stitched together and manually tested at the register transfer level, where the process is much slower and more error prone.

The great myth of HLS is that it’s only good for datapath-based designs. In fact, tools based on SystemC can accurately model all aspects of a design including the algorithm or datapath and the interfaces—typically much more control oriented. ANSI-C-based tools are severely limited in this area because the language has no way to represent time. As a result, an accurate interface or controller cannot be modeled or simulated without some proprietary extension.

HLS design teams have completed myriad control-based designs such as solid-state-disk (SSD) controllers for portable hard drives, High-Definition Multimedia Interfaces (HDMIs), direct-memory-access (DMA) controllers, and more. These control-based designs are integrated with more datapath-oriented blocks. The entire system can be simulated at high speed in one language.

High-level synthesis is a technology that’s becoming mainstream. The dramatic shifts in economic conditions have forced chief executive officers, engineering vice presidents, design managers, and designers to think differently. Today’s focus is on doing more with less without losing the innovative spirit. Leading HLS tools have already been used to produce hundreds of designs to ship products that are in living rooms across the world. For the first time in at least a decade, the cost of design can start to come down while design teams provide expected quality of results in far less time than RTL code.

Brett Cline is vice president of marketing and sales for Forte Design Systems. Before joining Forte in 1999, he was director of marketing at Summit Design. Cline has held positions in development, applications, and technical marketing at Cadence Design Systems and General Electric. He holds a BSEE from Northeastern University in Boston.

Mike Meredith is vice president of technical marketing for Forte Design Systems. He also serves as president of the Open SystemC Initiative. His more than 20 years of EDA experience includes the development of printed-circuit-board layouts, schematic capture, timing-diagram entry, verification, and high-level synthesis tools. Previously, Meredith spent 10 years doing embedded design in the biomedical and industrial-automation industries. He is a contributor to two books on ESL methodology and high-level synthesis. Meredith holds three US patents in the areas of timing diagrams and the timing analysis of electronic circuits.