This technical digest discusses the spectrum of verification and debug tools that the ISE® Design Suite puts at your disposal.
Featured White Papers
Evolving the Coverage-driven Verification Flow
Verification methodology has undergone dramatic changes over the past decade. The realization that larger and more-complex designs required more and more verification effort, coupled with shrinking schedules, spawned new languages specifically tailored for verification and tools intended to make the verification process more predictable and efficient.
Power Consumption at 40 and 45 nm
At 40 and 45 nm process nodes, power has become the primary factor for FPGA selection.
Accurately Analyzing Power in a Simulink Software Model-Based Design Flow
Frequency, run time, and area utilizations are widely used as benchmarking metrics to gauge quality of results (QoR) for FPGA designs and tool performance.
Capabilities to Maximize Productivity for FPGA Debug and Verification
Whether your task is to verify the functional correctness of a design, ensure adequate timing performance, or to quickly bring up a hardware platform in the lab environment, efficient verification and debug typically requires evaluating the design from multiple perspectives—ranging from high-level functional characteristics to low-level performance details—each at different phases of the design flow.
The PSP Model in RF CMOS Design
This white paper explains the technology behind Penn State Philips (PSP) transistor models and how they relate to actual device behavior.
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EE Catalog Tech Videos
A Historical Perspective on Semiconductors and Moore's Law
Intel Corporation legend, former CEO, and Chairman of the Board Craig Barrett discusses his personal career path from a Stanford Associate Professor, to Silicon Valley consultant, to a 35-year career inside one of the globe's most prominent players in technology. His talk concentrates on Moore's Law and the myriad factors in place to ensure its continued progeny.
Value Shifts In The Semiconductor Supply Chain
System-Level Design discusses where the money has shifted in the semiconductor supply chain with Synopsys, eSilicon, TSMC and Avago.
Challenges At 32nm And Beyond
Wally Rhines, chairman and CEO of Mentor Graphics, talks about what’s changing in design, the effect of low power, and who’s going to be doing the most advanced designs.
Tesla: The Ultimate Low-Power Design
When your battery pack alone costs $30,000 and you get 200 miles per charge, you’ve got to be looking for ways to save power. The Tesla roadster is crammed with parts from many Silicon Valley companies, all designed to draw as little power as possible. But there’s still much more work to be done.
Artificial Intelligence: This Time It’s For Real
AI used to be the stuff of science fiction, but cheap processing power and storage has made it a reality. To find out what’s being developed, System-Level Design (www.chipdesignmag.com/sld) tracked down Rachel Goshorn, assistant professor of System Engineering at the Graduate School of Engineering and Applied Science in the Naval Postgraduate School in Monterey, Calif. Check out what she has to say.
New Memory Technology Ahead
Christophe Chevallier, vice president of engineering at Unity Semiconductor, sat down with System-Level Design Contributing Editor Pallab Chatterjee to talk about multilayer technology that could boost chips to more than a terabyte using standard CMOS processes.
Saving Power By The Milliwatt
Power budgets may look small, but the amount of power that can be saved with different design approaches will surprise you.
Calendar of Events
Multicore Expo
San Jose, CA April 26-29, 2010 http://www.multicore-expo.com/