White Paper on PowerEN™

> A2 Core, full 64 bit based on Power Architecture® technology and support Power ISA 2.06

> 2.3GHz 45nm SOI with 16 cores and 64 Threads

> Low power, highly scalable design - 25-75W chip at full frequency

IBM announced a new IBM PowerEN™ as a new 64 bit architecture based on Power Architecture® technology and support Power ISA 2.06 to address the converging market between the network and servers.

Delivering Synthesizable Verification IP for Test Benches

High-level verification languages and environments such as e/Specman, Vera and now SystemVerilog, as used in VMM or OVM, may be the state-of-the-art for writing test bench IP, but they are not synthesizable for developing models, transactors and test benches to run in FPGAs for emulation and prototyping. So engineers wishing to move verification assets onto FPGAs have been designing with RTL, the same old slow, resource-intensive and error-prone way.

But now, with the introduction of modern high-level languages for synthesizable verification IP, engineers can design test benches, models and transactors at a high level of abstraction and with extreme reuse, but they can also synthesize them onto FPGAs – and they can do this as easily as they do today in simulation-only verification environments. Imagine running your test benches, models and transactors at tens of MHz.

This White Paper outlines important attributes of, and the applications for, modern high-level synthesizable verification environments. Using the example of a test bench for an Ethernet MAC, the paper compares the implementation of a synthesizable test bench done with Bluespec’s BSV with a non-synthesizable reference test bench done with SystemVerilog VMM – and it demonstrates that a synthesizable test bench can be implemented with fewer lines of code than using state-of-the-art SystemVerilog.

Creating Multi-Time-Domain ATE Test Programs for SOC Device Designs

Creating Multi-Time-Domain ATE Test Programs for SOC Device Designs [company]

High Performance Packet Processing in a Multicore Environment

Moore’s law does still hold, but processor vendors are rapidly turning to use the additional transistors to create more cores on the same die instead of increasing frequency since this not only gives more chip performance but also decreases the power consumption (watt/mips). This paper starts by describing the widely accepted multiprocessing software design models, and some of their benefits and drawbacks.

The Significance of Intel’s Core i7 to Embedded Computing

At the Consumer Electronics Show (CES) on January 7, 2010, Intel® announced 27 new processors in its Core® i3, Core® i5 and Core® i7 families. Significantly for the embedded industry, twelve of these were targeted specifically at embedded applications. Early indications are that the Core i7 will offer either more processing performance per watt compared with earlier products (estimated at around 20%), or lower power consumption per unit of processing performance than its predecessors.

Whitepaper on Stride and Prefetch feature in ISA 2.06

POWER stands for Performance Optimization with Enhanced RISC. Power architecture is synonymous with performance. Introduced by IBM in 1991, POWER1 was a superscalar design that implemented register renaming andout-of-order execution.

Hypervisors Thrive with Power Architecture

In concert with the inexorable demand for increasingly sophisticated functionality in embedded systems, semiconductor designers and systems software providers are creating novel methods to break through the recent flattening in Moore’s performance curve.

ARM DS-5 Examples -- Import a Linux application example into Eclipse

So you have created your ARM targeted Linux application but, now you need to debug or add features to it. This tutorial demonstrates the ease of importing an existing Linux project into ARM’s Eclipse based DS-5 environment. See this and more at www.youtube.com/armflix.

Hotspot Parallelization of C-Code to X86 or FPGAs

Check out the implemenation as the system renders three types of streaming videos. This parallelization approach maintains both the functional and interconnects of the original C-code. It is tauted as a muliticore solution. Compaan is a company based in The Nertherlands: www.compaandesign.com

Digital Microscope with Great Optics

Dino Lite makes handheld, USB cameras. What makes them of interest is the of CMOS image sensors combined with very powerful (5x to 200x) optical lens. That optical range is impressive. Be sure to see the pinkish bolt and the ants.

e-Books and Print on Demand at Springer

Listen to what Charles Glaser, Senior Editor the book giant Springer, has to say about the growing trend in e-books and print-on-demand publishing. Monday 14Jun10 at the Design Automation Conferene (DAC) in Anaheim, CA

Optical Magnification Counts

This is the first part of my brief video on digitial microscopes from Dino Lite. www.bigc.com

The EDA Polka Band

Warm-up act to Gary Smith's trends talk on the Monday (6/14) morning Pavilion Panel at DAC.

Nabto shows up at ESC

Ran across Nabto at the Embedded Systems Conference in San Jose, CA this week. Their embedded IP makes it possible for a small processor to serve as a webserver and create a connection through your firewall to stream content. From an engineering perspective it's pretty cool. For a journalist it's earthshaking. It simplifies connectivity without damaging security.