Creating Multi-Time-Domain ATE Test Programs for SOC Device Designs

Modern chip designs frequently involve System-on-Chip architectures as ever increasing levels of
integration brings more functionality on board. One of the ramifications of this increased system
integration is increasingly complex clock schemes throughout the chip. In the best case
scenario, clock trees distribute clock signals from common points to all the synchronous
functional elements on the chip and often include simple dividers to create the specific
frequencies required by each function block.

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