Get Your ASICs and SOCs Off the Bus!

The choice of hardware-interconnection mechanisms among processor blocks in an SOC affects communication performance and silicon cost. The default on-chip communications choice for most ASIC and SOC design teams is the global bus or a bus hierarchy, however this choice automatically incurs many performance and design problems. There are other choices that may be more appropriate for today’s nanometer ASIC and SOC designs. These choices match well with communications concepts frequently used by software developers. For example, message-passing software communications have a natural correspondence to data queues. Message passing can be implemented using other types of hardware such as bus-based hardware with global memory.



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