Real Intent Boosts Design Verification Productivity

Santa Clara, California – February 22, 2011Real Intent Inc., the leader in automating the intelligence of formal techniques for design verification signoff, today announced the immediate availability of Ascent™ Lint Version 1.4.

Ascent Lint is the industry’s fastest and most accurate solution for performing syntax and semantic lint checks for complex SoC designs. Version 1.4 includes significant new functionality to improve design productivity and the comprehensiveness of rule checking.

Ascent Lint 1.4 features a new capability to generate incremental reports, which compare violation differences between runs. Incremental reporting saves designers significant time by directing attention to new violations since the last check. Other productivity features include an enhanced capability to waive violations from the command line, design source files or graphical user interface, as well as scope-based lint analysis and reporting, which allows designers to focus on specific portions of the overall design.

Comprehensiveness is improved in version 1.4 with new rules for arithmetic data path checking, dubious logic modeling and RTL (Register Transfer level) coding policy. In addition, a new rule set has been added to analyze the integrity of netlists.

“Ascent Lint has been consistently outperforming the competition in runtime by more than 10x since its initial release,” commented Pranav Ashar, CTO of Real Intent. “In many evaluations, it has been the only tool with acceptable run time for designs upwards of 10 million gates. The focus in Ascent Lint 1.4 has been on providing industry-leading user productivity features. To that effect, the new release adds incremental reporting, scope-based analysis, and enhanced waiver capabilities to the already compelling platform. Customer feedback has been very positive. All indications are that Ascent Lint 1.4 is far ahead in performance, capacity, usability and quality of results.”

Pricing and Availability
Ascent Lint 1.4 is available now. For pricing information, please contact

About Real Intent‘s Automatic Verification Software
Real Intent’s automatic verification families include Ascent for early functional verification, Meridian™ for early Clock Domain Crossing (CDC) and Design for Test (DFT) verification, and PureTime™ for comprehensive constraints validation with glitch-aware exception verification.

About Real Intent
Real Intent is the leader in automating the intelligence of formal techniques for electronic design verification signoff. Its software dramatically improves functional verification efficiency and design quality for ASICs and FPGAs devices and is used by design and verification teams worldwide. Follow @RealIntent on Twitter.

Contact Information

Real Intent

990 Almanor Ave
Suite 220
Sunnyvale,, CA , 94070

tele: 408-830-0700
fax: 408-737-1962

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