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A Look into the Future of Chip Design

Looking into the future of chip design requires a look back at the past.  In the past, silicon area was expensive and design teams optimized for area to get as good performance as they could without wasting too much area.  Then gates became comparatively plentiful and timing was the big challenge, using that area to get as high performance a design as possible.

Today, power is the big limiter and the biggest challenge.  Design teams now sacrifice area to reduce power.  For example, they add specialized blocks to decode MP3 that are never used when we are not listening to music and which, apart from using more power, could perfectly well be handled by the main control processor.

Power is rather different from timing.  If a designer wants a chip to run at a particular clock rate, then many blocks on the chip must independently be able to do so.  Although challenging, it is possible to work out the required performance for every block and pass that on to the designer as a constraint.

Power is a chip-level problem.  It is worse due to different modes too –– it is not acceptable to have a cell phone with three-hour talk time and four-hour standby time, or 48 hours of standby time and 30 minutes of talk time.  This makes it almost impossible to divide the power budget up among blocks before starting the design.

Furthermore, as chips have hundreds of millions of ASIC gates, along with huge amounts of memory and other blocks, dividing the design up into lots of supposedly independent blocks and handling them separately no longer works for timing either.  When physical design is done, there is too much of a difference between timing values predicted in synthesis –– without any physical information and actual timing values ––after place and route (P&R), once wire lengths and interactions are finally known.

Synthesis and P&R must be done using the same hierarchy.  In many cases, physical design is done flat.  This means synthesis must be done “flat” in the sense of synthesizing the entire chip to placed gates –– nothing less gives a designer accurate enough timing.  Many chips are too big for physical design to be done flat.  As a result, they are handled as a number of large blocks.  Synthesis must be done at the level of one (or even a few) of these large physical hierarchy blocks.  This design trend is called Chip Synthesis, a different design strategy than traditional synthesis.

The move to Chip Synthesis is a wave that is currently underway as the most advanced semiconductor companies switch their most advanced and complex designs to this chip-level methodology, switching from the technology of the last 20 years.  That is, the tactic of partitioning the design into many small blocks and then stitching them together just before P&R.  For smaller chips, off the bleeding edge, the old approach will live on for a time, because every designer knows how to do it, the EDA infrastructure is in place and so on.

But just as a race car driver needs different technology to win a Formula-1 race or to drive to the store around the corner, leading-edge designs need to adopt the most effective technology if they are going to win.  A design platform such as our Chip Synthesis is the future of chip design.

Paul van Besouw--oasys--headshot

Paul van Besouw is president and CEO of Oasys Design Systems of Santa Clara, Calif., noted for its Chip Synthesis platform that offers chip-level power analysis and the ability to synthesize a design from RTL with power constraints.  Demonstrations of RealTime Designer, a tool to manage power at the chip level, will be demonstrated in Booth #2031 during DAC. www.oasys-ds.com paulvb@oasys-ds.com

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