SiSoft, Ericsson and SiGuys Present Case Study of Virtual Prototype Analysis
Virtual System Model Supports 48 Hour Turnaround from PCB Layout Changes to Updated Results
Santa Clara, CA – February 1, 2012 – Signal Integrity Software, Inc. (SiSoft™) will present a paper entitled “Simulating Large Systems with Thousands of Serial Links” at DesignCon 2012 today. The paper will be co-presented with Sergio Camerlo, an engineering director with Ericsson Silicon Valley (ESV) and Donald Telian of SiGuys. The paper details the creation of a fully populated virtual system model generated through the use of Virtual Prototype Analysis (VPA) that can be used to perform many of the tests that would normally require a physical prototype. Link behavior can be extensively characterized and optimized before prototypes are built. The use of a virtual system model supports a 48 hour turnaround from PCB layout changes to updated results, versus a turn time of weeks for a physical prototype.
“Virtual prototype analysis provides substantial amounts of data,” noted Donald Telian of SiGuys. “Key performance metrics can be mined to identify important system-level trends. For example, we can identify how backplane routing layer affects eye height across thousands of links, taking into account all the complex interactions between the different elements of each link. This provides deep insight into system behavior and supports critical decisions like whether to add, remove or rearrange routing layers in the backplane. Simulation technology has matured to the point where we can perform enough simulation and post-processing to characterize a virtual system model as though it were a physical prototype. Since the virtual system model is fully controllable and observable, we can run tests on a virtual system that cannot readily be performed on a physical system. These tests include confirming system-level connectivity, balancing and optimizing equalization on a per-channel basis and quantifying design margins against performance targets.”
“SiSoft has always collaborated with key customers to develop advanced signal integrity methodologies,” said Barry Katz, SiSoft’s president and CTO. “Our EDA tools provide an automated, structured methodology for system-level signal integrity. It isn’t running a simulation and getting a waveform that’s important – what’s important is taking the simulation output and determining whether the design will work, or not, and with how much margin. Our EDA tools post-process simulation results to extract key compliance and performance metrics that give designers that information.”
“Virtual Prototype Analysis (VPA) is the result of scaling our methodologies to the full system level, so that key performance data from thousands of signals can be compared and mined,” Barry Katz noted. “Deep collaboration with customers like Ericsson is key to proving simulation technology at this scale.”
SiSoft will be demonstrating its Quantum Channel Designer (QCD) software and support for Virtual Prototype Analysis at DesignCon 2012. Key features of QCD enabling Virtual Prototype Analysis include:
- Accurate models and simulation algorithms
- Very large simulation database capacity
- Scalable high-performance simulation
- Automated reporting of key design and compliance metrics
- Front to back analysis automation (case generation, simulation, post-processing)
- Simulation database management (data mining)
About SiSoft™
SiSoft™ collaborates with system designers and their suppliers to create full solutions for system-level high-speed design, providing a combination of award-winning EDA tools, methodology development, model validation and consulting services. Quantum Channel Designer® is the Industry’s Premier Channel Simulator for the design and analysis of multi-Gigabit serial links and a DesignVision 2009 Award Winner. Quantum-SI™ is the leading solution for integrated signal integrity, timing and crosstalk analysis of high-speed parallel interfaces. SiSoft’s software products automate comprehensive pre- and post-route analysis of high-speed interfaces, detailing a design’s operating voltage and timing margins. Design Space Exploration lets designers explore hundreds of design tradeoffs automatically, quickly optimizing designs for cost, reliability and performance.
