LTE-Advanced Signal Generation and Measurement Using SystemVue

LTE-Advanced is specified as part of Release 10 of the 3GPP specifications and is now approved for 4G IMT-Advanced. This application note introduces key LTE-Advanced techniques, as well as how to use the Agilent SystemVue W1918 LTE-Advanced library to generate various downlink (DL) orthogonal frequencydivision multiple access (OFDMA) and uplink (UL) clustered DFT-spread-OFDM (DFT-S-OFDM) signal sources with MIMO, and to measure closed-loop throughput.

This application note also introduces LTE-Advanced enhancements to the MIMO channel models, which are available as simulation model set called the W1715 SystemVue MIMO channel builder. This optional model set facilitates simulation-based MIMO over-the-air (OTA) testing using real, observed antenna patterns and standard MIMO fading models, and overcomes a key challenge for 8-layer MIMO system analysis and verification.

Linking Early Mechatronic System Analysis to Physical Testing

Mechatronic system design creation and test development are often at opposite ends of a project's schedule. Benefits accrue in improved system quality and on-time delivery when design and test are pursued concurrently. This paper describes the technologies required to make concurrent design and test possible.

Best Practice Development Processes for Medical Device FPGAs

For FPGA developers working on designs for medical devices, one approach to dealing with regulatory uncertainty is to borrow heavily from design assurance processes in other safety-critical industries, such as avionics, where standards are well established. These well-established standards mandate a development flow that is controlled, auditable and perhaps most important, specific to the requirements of hardware engineering. While following such a flow will not guarantee smooth sailing though every regulatory approval process for FPGA devices bound for medical applications, it is consistent with basic regulatory intent - to demonstrate to auditors that complex devices meet their requirements and perform well under all foreseeable conditions.

Direct Power MOSFET Capacitance Measurement at 3000 V

Learn how to make power MOSFET capacitance measurements at up to 3000 V of DC bias.

Common Pitfalls in PCI Express Design

PCI Express is a point-to-point communications interface. It is neither an evolved nor enhanced form of PCI or PCI-X, but, essentially, a high speed, low voltage, differential serial pathway for communication between two devices, although it uses the same programming model as its predecessors.

Increasing Revenue Through Continuously Optimized Data Center Management

Most businesses are completely dependent on technology, and the impact of using non-optimized technology can be directly measured in their revenue. Why? Because as widespread dependence on technology has grown, the size and complexity of the technology’s environment has grown in a non-linear manner.

Designing For Low Power

Power consumption is becoming an increasingly important variable when it comes to calculating OPEX and carbon footprint for telecom infrastructure projects.

Parasoft approaches comprehensive testing for embedded software

The explosive growth of portable and wireless technology is a driver for similar growth in embedded software development....

Automating embedded software testing with Electric Cloud

The problem comes in when you are not a software-centric company. The 2012 UBM Embedded Market Survey showed that, for the first time, QA engineers are becoming a significant portion of embedded software teams, and while the quality of debugging tools is still the top area for improvement, engineers seem to be getting more confident with what is available. However...

Strategy And Technology: One On One With Wally Rhines

Mentor's Chairman and CEO sounds off about where the IC design challenges are, what needs to be done to fix them, and what new opportunities will unfold.

One-On-One: Jack Harding

eSilicon's CEO talks with System-Level Design about changes in design at advanced nodes, the power of 2.5D and 3D stacking, and how the semiconductor supply chain is changing.

One-On-One: Naveed Sherwani

Open-Silicon’s CEO talks with System-Level Design about getting the business priorities of designing a complex SoC in line with the technology; why getting chips out the door on time is critical and why it’s not happening.

Walter Ng, GLOBALFOUNDRIES at DAC 2011 - IP Talks presenter

Interview with Walter Ng, Vice President, IP Ecosystem, GLOBALFOUNDRIES. DAC 2011. Demonstrating 32/28nm design, 20nm technology. Design Enablement, ChipEstimate.com IP Talks 2011

Verification: What's in Your Wallet?

This DAC Pavilion Panel explores technical and business issues related to SoC verification by panelists from ARM, AMD and Qualcomm.