print

Aldec And Synthworks Deliver Randomization And Functional Coverage Capabilities To Vhdl Designers With Os-Vvm™

news_1

Aldec, Inc., in collaboration with SynthWorks Design Inc., announces the availability of Open Source – VHDL Verification Methodology (OS-VVM™), underscoring the partnership’s commitment to provide continued support to the VHDL design community. OS-VVM delivers advanced verification test methodologies, including Constrained and Coverage-driven Randomization, as well as Functional Coverage, providing advanced features to VHDL design engineers while enabling them to continue to develop using VHDL.

Contact Information

Aldec, Inc.

2260 Corporate Circle
Henderson, NV, 89074
USA

tele: 702-990-4400
fax: 702-990-4414
sales@aldec.com
www.aldec.com

Share and Enjoy:
  • Digg
  • Sphinn
  • del.icio.us
  • Facebook
  • Mixx
  • Google
  • TwitThis