AMIQ: Come and learn about our code development and analysis tools in Booth #1804 at DAC
You are invited to visit us at DAC
June 3-7, 2012 in San Francisco at the Moscone Center
Booth # 1804
Those of you, who have known us for a while, may notice that we have changed our logo.
Our new logo has been launched this month and is replacing the previous one, which was created in 2003. We wanted a logo that better represents the company values and directions of development.
The AMIQ team is friendly and creative and has a passion for bringing to life sharp ideas. These qualities are reflected by the new shape of the logo as well as by its dark blue color.
The dark blue also captures our focus on deep knowledge and domain expertise, excellence, integrity, and commitment to our customers worldwide. The red color echoes AMIQ’s dynamism and passion, qualities that have been passed on by the company’s three founders since its inception.
Learn more about our solutions:
With DAC – the premier event for the EDA industry – almost here, we hope to include AMIQ EDA on the list of exhibitors you want to visit. We will be showing our code development and analysis tools that help improve design and verification productivity, enabling you to complete your projects faster. Here are a few highlights:
Design and Verification Tools (DVT) Eclipse IDE
- Increases the speed and quality of code development
- Simplifies legacy code maintenance
- Lowers language and methodology learning curve
DVT Eclipse, the first Integrated Development Environment (IDE) for e, SystemVerilog, and VHDL, is built upon the Eclipse platform and comprises an IEEE standard-compliant parser, a smart code editor, and a complete suite of tools that help with code readability, navigation, documentation, and debugging. It integrates with all major simulators, revision control systems, and bug tracking engines. DVT Eclipse supports UVM, OVM, and VMM and provides advanced capabilities like project and code templates, dedicated wizards, construct autocomplete, simulation log recognition, and UVM/OVM compliance checking.
Verissimo SystemVerilog Testbench Linter
- Improves testbench code reliability, functionality, and maintainability
- Enables verification groups to implement best coding practices and their own specific guidelines.
- Reduces code maintenance costs
The Verissimo linter performs a thorough static analysis of the source code and signals improper language, semantic, and styling usage, as well as verification methodology violations. It includes a comprehensive library of generic SystemVerilog and UVM/OVM checks. Verissimo also allows users to customize their own rule sets by selecting from the hundreds of built-in checks those that match better their needs, or create new rules according to their requirements by using a dedicated Java API. Verissimo can run standalone in batch mode or integrate with the DVT Eclipse IDE. Users can easily read the linter’s error and warning messages in the DVT GUI, as well as filter them by category, severity, and source location; or jump directly to the problematic source code using DVT’s navigation capabilities such as hyperlinks.
We look forward to seeing you at DAC.
The AMIQ EDA team