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Real Intent Leads in Speed, Capacity and Precision with New Releases of Ascent Lint and Meridian CDC Verification Tools; Demos Set for 49th DAC

SUNNYVALE, Calif. – May 29, 2012 – Real Intent, Inc., the leading provider of software products that accelerate Early Functional Verification and Advanced Sign-off of electronic designs, announced today the release of version 4.1 of its Meridian™ Clock Domain Crossing (CDC) analyzer and the release of version 1.5.1 of its Ascent™ Lint tool. These new releases provide significant advances over the 2011 versions of the software.

Real Intent’s software products solve challenging SoC verification and sign-off design problems with speed that no other company can match. The tools are capable of handling full-chip designs in excess of 100-million gates flat, with no compromises in accuracy or performance.

“These new releases deliver deeper analysis without sacrificing speed or capacity and support our technical leadership in Early Functional Verification and Advanced Sign-off,” stated Prakash Narain, CEO of Real Intent. “Our low-noise reporting avoids burying designers with superfluous or incorrect results despite the ever-increasing complexity of designs. The dramatic growth in our revenue and customer base is a testament to our ability to accelerate design verification and sign-off.”

Ascent Lint Delivers Advanced Debugging and Faster Analysis for RTL Designs

The latest Ascent Lint brings greater ease of use and even faster turnaround time to the industry’s fastest, high-capacity, low-noise lint analyzer. The updated debugger GUI allows editing design source files, rule configurations, and inserting waivers from the violation line. Re-invoking lint analysis from the debugger GUI is dramatically faster with shorter turnaround times. Over 50 new SystemVerilog, Verilog, VHDL and netlist rules have been added.

Meridian CDC Advanced Features and Deeper Analysis

The newest Meridian CDC furthers Real Intent’s leadership in CDC analysis. It excels in speed, capacity and low noise analysis of asynchronous clock domains in SoC designs with a new formal engine which goes further and faster to find hidden CDC problems. Design language support has been extended to include the SystemVerilog synthesizable subset. The user experience has been enhanced substantially in a new front-end interface which incorporates SpringSoft’s Verdi Automated Debug System, and delivers improved analysis setup, debug features and ease of use.

Real Intent at the Design Automation Conference (DAC) 2012, San Francisco

Demonstrations of the Ascent and Meridian products are set for Monday through Wednesday, June 4-6, 2012, 9:00 am to 6:00 pm, at Real Intent’s DAC booth #926. To register for a demonstration click here.

About Real Intent

Real Intent is the leading provider of EDA software to accelerate Early Functional Verification and Advanced Sign-off of electronic designs. The company provides comprehensive CDC verification, Advanced RTL Analysis and Sign-off solutions to eliminate complex failure modes of SoCs. Real Intent’s products lead the market in performance, capacity, accuracy and completeness. Please visit www.realintent.com for more information.

Contact Information

Real Intent

990 Almanor Ave
Suite 220
Sunnyvale,, CA , 94070

tele: 408-830-0700
fax: 408-737-1962
info@realintent.com
www.realintent.com

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