Write assist techniques are now commonly used to lower the minimum operating voltage (Vmin) of an SRAM. One of the key reasons to push the SRAM Vmin lower is to enable efficient Dynamic Voltage and Frequency Scaling (DVFS) to save power. In this paper, we discuss the basics of SRAM faliure mechanisms, fundamentals of write assist techniques, ARM® Artisan® Low Voltage Memory Compilers with the write assist feature and results from GLOBALFOUNDRIES 28nm-SLP memories.
Write Assist in Low-Voltage SRAMs
EECatalog Tech Videos
Featured White Papers
Packet processor design teams face increasingly difficult challenges as they seek to provide their network equipment manufacturers with state-of-the-art devices. The interrelated system-level trade-offs include performance, pin count, and area, and are all ultimately limited by power consumption considerations. To successfully compete, network chip vendors must consider end-to-end solutions for system architects and developers. In turn, as OEMs introduce multi-terabit systems, they must aggregate multiple 100 Gbps ports on each line card or risk falling behind the performance curve.
The MIL-STD-1553 serial data bus is widely used for control purposes in avionics, aircraft and space systems. Forty years since its release, 1553 is evolving from traditional integrated circuits (IC) to intellectual property (IP) cores integrated with Field Programmable Gate Array (FPGA) logic. The history of MIL-STD-1553, the advantages and requirements of 1553 IP cores compared to standard ICs, and IP core design best practices are discussed in this white paper.
Field Programmable Gate Arrays (FPGAs) are semiconductor devices that are programmed after manufacturing to accomplish application specific functionality. FPGAs experienced rapid technology advancement in the 1990s, and today are found in a vast variety of products ranging from simple consumer items to highly complex military systems.
FPGA-based prototyping is gaining popularity because it provides an economical way to functionally verify an ASIC design by creating a prototype that runs close to "at speed." FPGA-based prototypes also provide a great platform for early system software development. However, FPGA architectures include resources, building blocks, power circuitry, and clocks that are fundamentally different from those of an ASIC. With over 70% of today's ASICs and systems-on-chips (SoCs) being prototyped in an FPGA, designers are looking for ways to ease the creation of FPGA-based prototypes directly from the ASIC design source files.
An FPGA Approach to Implementing Time-Critical Functions in Multi-Sensor Mobile Designs.
Learn about FPGA-based system design for embedded computing I/O signal processing applications. Free your CPU by rapidly computing custom FFTs, SERDES, logic, and more. We discuss implementing co-processors, like Acromag Virtex-6 FPGA modules with high-speed PCIe/GbE interconnects, using IP cores and software development tools for higher performance and flexibility.
Kintex 7 FPGA family: High Performance DDR3 memory throughput achieved by optimization of the memory controller
Taking full advantage of the performances of the 7 Series FPGAs can be done by using the high speed memory controller from Barco Silex, which has been reworked to achieve the highest frequency and efficiency.
EECatalog Tech Videos
In our third interview at the Design Automation Conference in Austin, Texas, John Blyler of Chip Design Magazine talks with Dennis Bibeau of Infotech about the importance of collaboration across all disciplines in achieving innovative chip design.
Chip Design's John Blyler interviews Cristian Amitroaie, CEO of AMIQ (http://www.amiq.ro) on the importance of code integration and the Eclipse platform At the Design Automation Conference in Austin, Texas.
In our first interview at the Design Automation Conference in Austin, Texas, John Blyler talks with Zhihong Lu of Proplus (http://www.proplussolutions.com/en/contact/) about the problems and potential of innovation in chip design through statistical analysis.
In our fourth interview this week at the Design Automation Conference in Austin, Texas, EiC John Blyler of Chip Design talks with Mike Gianfagna, Vice President of Corporate Marketing at Atrenta, about the growing competition and advances in RTL Signoff.
GigOptix demonstrates 40G DQPSK with revolutionary TFPS polymer modulator
This video was provided by IEEE.tv's coverage of IMS 2012 in Montreal. Material was created by Ben Zarlingo and presented by Bruce Erickson of Agilent Technologies. http://www.agilent.com/find/sa
Sarath Kirihennedige, Sr. Manager Product Engineering at Real Intent, speaks with Graham Bell about how design constraints (SDC) are currently developed, what are the problems with the current approach and what a complete Constraints management and verification solutions looks like.