July - 2014
- Why Don't Software Programmers like Comments?
Cristian Amitroaie, CEO of Amiq, talks with John Blyler about Specador, a automated HTML documentation tool for chip design and verification engineers. This tool generates meaningful documentation even from poorly documented source code, as it actually compiles the code and can generate cross-link class inheritance trees, design hierarchies, and diagrams. The need for this functionality lead to an interesting discussion about the software programming process and why programmers rarely document their own work.
June - 2014
- Why IP Providers Need the New 1149.1/JTAG
Intellitech's CEO CJ Clark explains why the latest JTAG update brings much needed capabilities to IP providers and IC developers alike.
April - 2014
- Imec’s mm Wave Motion Sensing Technology
Motion sensing applications with mm wave technology at Imec is the topic of this interview between Liesbet Van der Perre, Imec Program Director of Wireless Communication, and John Blyler, VP and CCO at Extension Media.
December - 2013
- Mentor’s Wally Rhines – Learning Curve; Golden 28nm, IoT Innovation and Systems Engineering
Wally Rhines, Chairman and CEO of Mentor Graphics, talks about Moore's Law in light of the Learning Curve; 28nm as the golden node; critical need for IoT innovations; and why systems engineering often fails.
June - 2013
- Code integration facilitates chip innovation
Chip Design's John Blyler interviews Cristian Amitroaie, CEO of AMIQ (http://www.amiq.ro) on the importance of code integration and the Eclipse platform At the Design Automation Conference in Austin, Texas.
- Collaboration is the key to chip innovation
In our third interview at the Design Automation Conference in Austin, Texas, John Blyler of Chip Design Magazine talks with Dennis Bibeau of Infotech about the importance of collaboration across all disciplines in achieving innovative chip design.
- Innovating with Statistical Analysis
In our first interview at the Design Automation Conference in Austin, Texas, John Blyler talks with Zhihong Lu of Proplus (http://www.proplussolutions.com/en/contact/) about the problems and potential of innovation in chip design through statistical analysis.
- RTL Signoff turns competitive
In our fourth interview this week at the Design Automation Conference in Austin, Texas, EiC John Blyler of Chip Design talks with Mike Gianfagna, Vice President of Corporate Marketing at Atrenta, about the growing competition and advances in RTL Signoff.
November - 2012
- GigOptix-40G DQPSK Demonstration
GigOptix demonstrates 40G DQPSK with revolutionary TFPS polymer modulator
September - 2012
- Cost-Effective Millimeter Signal Analysis Approaches | Agilent Technologies
This video was provided by IEEE.tv's coverage of IMS 2012 in Montreal. Material was created by Ben Zarlingo and presented by Bruce Erickson of Agilent Technologies. http://www.agilent.com/find/sa
- SDC Management and Verification: What's Missing?
Sarath Kirihennedige, Sr. Manager Product Engineering at Real Intent, speaks with Graham Bell about how design constraints (SDC) are currently developed, what are the problems with the current approach and what a complete Constraints management and verification solutions looks like.
- John Blyler Interview on ChipEstimate.TV
Sean O'Kane, Producer/Host ChipEstimate.TV interviews: John Blyler, Editor-in-Chief, Chip Design
- Synopsys Discusses its New DDR4 Memory Interface IP
Sean O'Kane from ChipEstimate.com interviews Navraj Nandra about the Synopsys' DesignWare DDR4 IP product release. They discuss DDR4 SDRAM, its market, and their predictions for DRAM.
Navraj Nandra, Synopsys and Sean O'Kane, ChipEstimate.com
August - 2012
- IMS 2012 Keynote on Integrating Design and Test
Dr. Mark Pierpoint delivers the IMS2012 MicroApps Keynote address: As global competition increases, the need to produce the next state-of-the-art product faster has driven changes in how EDA and test instrumentation work together. Gone are the days when a design could be thrown over the wall to production. The next generation of communications protocols have barely been labeled "standards" when products using them have hit the streets. To produce better communications products faster requires that the line between EDA and test be blurred and new synergies between them created...
- Paul Estrada discusses the benefits of integrated analog FastSPICE with Tanner EDA tool suite
Paul Estrada - CTO of Berkeley Design Automation - shares his perspectives on the benefits to users by integrating BDA Analog FastSPICE within the analog mixed-signal design tools offered by Tanner EDA.
- Semicon West - Jim Feldhan interview
John Blyler, Editor-in-Chief, Chip Design and Embedded Intel magazines interviews: Jim Feldhan, President, Semico Research.
- Semicon West - Karen Lightman interview
John Blyler, Editor-in-Chief, Chip Design and Embedded Intel magazines interviews: Karen Lightman, Managing Director, MEMS Industry Group
- Semicon West 2012 - Ludo Deferm interview
John Blyler, Editor-in-Chief, Chip Design and Embedded Intel magazines, Sean O'Kane, Producer/Host ChipEstimate.TV interviews: Ludo Deferm
- 3D EDA Readiness at Cadence
Samta Bansal, product marketing manager, Cadence, talks about the challenges facing EDA vendors with the commercialization of 3D ICs, and how Cadence is leading the charge.
July - 2012
- KLA-Tencor 450mm-Capable Surfscan® SP3 Systems
At Semicon West 2012 KLA-Tencor Corporation (NASDAQ: KLAC) talked with New Tech Press about new installations of the Surfscan® SP3 450, the first process control systems capable of handling and inspecting 450mm wafers. Marketing division head Amir Azordegan siad the system is a precursor for the industry wide acceptance of 450mm process development. He claimed the Surfscan SP3 450 delivers critical capability for manufacturers of 450mm process equipment, such as wet clean tools, CMP pads, slurries and polishers, film deposition tools and annealing systems. KLA-Tencor has received multiple orders for the tool and shipped six.
- Chipmakers Adopt Cymer’s SmartPulse™
New Tech Press sat down with Nigel Farrar, vice president of marketing and lithography Technology for Cymer, Inc.(Nasdaq: CYMI) to talk about the prospects of extreme UV process adoption, as well as new products including the SmartPulse™ data management tool, and focus drilling technology for ArF immersion light sources.
- Chris Mack goes deep (UV)
With all the excitement at Semicon West 2012 about the move to 450mm wafer manufacturing, New Tech Press decided to call up the Lithoguru, Chris Mack, to get a reality check on the news. As usual, Dr. Mack was more circumspect than excited. Mack was vice president of lithography technology for KLA-Tencor. before “retiring” to write, teach and consult in the field of semiconductor lithography. He has trained more than 2,000 lithographers from over 200 different companies around the world, and is an adjunct faculty member in the Electrical and Computer Engineering and Chemical Engineering Departments of the University of Texas at Austin. In January 2012 he become Editor-In-Chief of the Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3).
- Power and Reliability Sign-off
Power and Reliability Sign-off Using RedHawk and Totem in GlobalFoundries Advanced 28nm Low Power Process
- "New Verdi³ and the Verdi Interoperability Apps (VIA)", Mark Milligan, VP of Marketing, Springsoft
Mark Milligan, VP of Marketing at Springsoft, speaks with Graham Bell from Real Intent about the new Verdi³ debug environment and the VIA exchange for the integration of verification tools from partners such as Real Intent. The interview took place at the Real Intent DAC 2012 booth in San Francisco in early June.
- “What is Driving Lint Usage in Complex SOCs?”, Jim Foley, R&D Manager, Real Intent
Jim Foley, R&D manager at Real Intent speaks with Graham Bell regarding what is driving RTL lint usage in Complex SOCs. This interview took place at the Real Intent DAC 2012 booth in San Francisco, CA in early June.
- "Real Intent Demos, and CDC Issues", Jay Littlefield, Sr. FAE
Jay Littlefield, Sr. FAE at Real Intent, discusses with Graham Bell the various demonstrations being shown at the Real Intent DAC 2012 booth. He goes on to mention what are some of the issue with verifying correct signal crossing between asynchronous clock domains.
June - 2012
- DAC 2012 Update on AMIQ's DVT IDE - New RTL Design Work Flow Support
AMIQ has been in the vanguard of supporting functional verification methodologies and testbench creation for years. The success verification engineers using AMIQ's "DVT" IDE product has been increasingly noticed by their RTL designer colleagues such that AMIQ is now adding new capabilities to DVT to support RTL design work flows. In this interview shot on the DAC 2012 expo floor, AMIQ CEO Cristian Amitroaie describes how they have extended the DVT IDE to address the needs of design engineers, including powerful new capabilities to refactor and visualize the code and signal flow. More on this product here: http://www.dvteclipse.com
- Cadence Pattern Matching and DFM signoff success
Luigi Capodieci, Director of Design for Manufacturing, R&D Fellow at GLOBALFOUNDRIES, discusses how they collaborated with Cadence on pattern-matching technologies to accelerate full-chip DFM signoff.
- The Next 25 Years of Innovation - DAC 2012 (Part 3)
Hear predictions for the next 25 years of innovation from attendees of the 49th Design Automation Conference.
- Richard Goering Talks With Naresh Sehgal (Intel) and James Colgan (Xuropa) About EDA in the Cloud
Richard Goering Talks With Naresh Sehgal (Intel) and James Colgan (Xuropa) About EDA in the Cloud