EECatalog Tech Videos
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The SmartFusion®2 system-on-chip (SoC) FPGA is differentiated from other FPGAs by its low power capabilities that enable orders of magnitude lower power operation for low duty cycle applications.
Kintex 7 FPGA family: High Performance DDR3 memory throughput achieved by optimization of the memory controller
Taking full advantage of the performances of the 7 Series FPGAs can be done by using the high speed memory controller from Barco Silex, which has been reworked to achieve the highest frequency and efficiency.
Write assist techniques are now commonly used to lower the minimum operating voltage (Vmin) of an SRAM. One of the key reasons to push the SRAM Vmin lower is to enable efficient Dynamic Voltage and Frequency Scaling (DVFS) to save power. In this paper, we discuss the basics of SRAM faliure mechanisms, fundamentals of write assist techniques, ARM® Artisan® Low Voltage Memory Compilers with the write assist feature and results from GLOBALFOUNDRIES 28nm-SLP memories.
Distributed systems range from simple multi-threaded applications to multi-slot chassis-based systems to networked clusters of servers. Topologies get more complex when these systems move into cloud-based environments, and more diverse when they involve machine-to-machine (or M2M) solutions. Providers of distributed system software solutions face a number of challenges in building, debugging and maintaining a set of connected applications. Managing these systems requires powerful modeling and a variety of management interfaces to meet a diverse set of needs. The services provided by a distributed system often require a high level of availability. The middleware frameworks that make up Enea Element address many of these challenges.
National Instruments uses multicore processors, user-programmable FPGAs, the high-throughput PCI Express system bus in PXI, and LabVIEW graphical system design software to address the business and technology challenges of high-frequency test and measurement. Read the white paper.
Traditional high-performance computing platforms are limited by the connection bandwidth and latency between the multiple computing elements needed to achieve the performance targets. For the embedded market, the difficulty is compounded by the demanding environmental requirements. The VPX standard resolves this limitation with a large number of high-throughput point-to-point connections between the processing elements in a rugged mechanical structure.
OpenVPX System Bandwidth: A comparison of 10Gb Ethernet Performance, Serial Rapid IO, and InfiniBand
This paper compares the bandwidth available to two common types of dataflow for systems based on the VITA 65 CEN16 central switched topology, using three different fabrics – Serial RapidIO (SRIO), 10 Gigabit Ethernet (10GbE), and Double Data Rate InfiniBand (DDR IB).
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EECatalog Tech Videos
GigOptix demonstrates 40G DQPSK with revolutionary TFPS polymer modulator
This video was provided by IEEE.tv's coverage of IMS 2012 in Montreal. Material was created by Ben Zarlingo and presented by Bruce Erickson of Agilent Technologies. http://www.agilent.com/find/sa
Sarath Kirihennedige, Sr. Manager Product Engineering at Real Intent, speaks with Graham Bell about how design constraints (SDC) are currently developed, what are the problems with the current approach and what a complete Constraints management and verification solutions looks like.
Sean O'Kane, Producer/Host ChipEstimate.TV interviews: John Blyler, Editor-in-Chief, Chip Design
Sean O'Kane from ChipEstimate.com interviews Navraj Nandra about the Synopsys' DesignWare DDR4 IP product release. They discuss DDR4 SDRAM, its market, and their predictions for DRAM.
Navraj Nandra, Synopsys and Sean O'Kane, ChipEstimate.com
Dr. Mark Pierpoint delivers the IMS2012 MicroApps Keynote address: As global competition increases, the need to produce the next state-of-the-art product faster has driven changes in how EDA and test instrumentation work together. Gone are the days when a design could be thrown over the wall to production. The next generation of communications protocols have barely been labeled "standards" when products using them have hit the streets. To produce better communications products faster requires that the line between EDA and test be blurred and new synergies between them created...
Paul Estrada - CTO of Berkeley Design Automation - shares his perspectives on the benefits to users by integrating BDA Analog FastSPICE within the analog mixed-signal design tools offered by Tanner EDA.
With the explosion of consumer electronics, designing for low-power has become an important design constraint and a key differentiating factor. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, both via automated tools as well as manually by the RTL designers. more