Taking full advantage of the performances of the 7 Series FPGAs can be done by using the high speed memory controller from Barco Silex, which has been reworked to achieve the highest frequency and efficiency.
Kintex 7 FPGA family: High Performance DDR3 memory throughput achieved by optimization of the memory controller
Contact Information
Barco Silex
Rue du Bosquet 7Louvain-la-Neuve, 1348,
Belgium
tele: +32 10 486 407
fax: +32 10 454 636
barco-silex@barco.com
www.barco-silex.com
EECatalog Tech Videos
Featured White Papers
Designing with FPGAs for Embedded Computing Speed and Flexibility
Learn about FPGA-based system design for embedded computing I/O signal processing applications. Free your CPU by rapidly computing custom FFTs, SERDES, logic, and more. We discuss implementing co-processors, like Acromag Virtex-6 FPGA modules with high-speed PCIe/GbE interconnects, using IP cores and software development tools for higher performance and flexibility.
SmartFusion2 Lowest Power FPGAs
The SmartFusion®2 system-on-chip (SoC) FPGA is differentiated from other FPGAs by its low power capabilities that enable orders of magnitude lower power operation for low duty cycle applications.
Kintex 7 FPGA family: High Performance DDR3 memory throughput achieved by optimization of the memory controller
Taking full advantage of the performances of the 7 Series FPGAs can be done by using the high speed memory controller from Barco Silex, which has been reworked to achieve the highest frequency and efficiency.
Write Assist in Low-Voltage SRAMs
Write assist techniques are now commonly used to lower the minimum operating voltage (Vmin) of an SRAM. One of the key reasons to push the SRAM Vmin lower is to enable efficient Dynamic Voltage and Frequency Scaling (DVFS) to save power. In this paper, we discuss the basics of SRAM faliure mechanisms, fundamentals of write assist techniques, ARM® Artisan® Low Voltage Memory Compilers with the write assist feature and results from GLOBALFOUNDRIES 28nm-SLP memories.
Enea Element®: Simplify Distributed Systems with Frameworks from Enea Element
Distributed systems range from simple multi-threaded applications to multi-slot chassis-based systems to networked clusters of servers. Topologies get more complex when these systems move into cloud-based environments, and more diverse when they involve machine-to-machine (or M2M) solutions. Providers of distributed system software solutions face a number of challenges in building, debugging and maintaining a set of connected applications. Managing these systems requires powerful modeling and a variety of management interfaces to meet a diverse set of needs. The services provided by a distributed system often require a high level of availability. The middleware frameworks that make up Enea Element address many of these challenges.
Redefining RF and Microwave Instrumentation Through Open Software and Modular Hardware
National Instruments uses multicore processors, user-programmable FPGAs, the high-throughput PCI Express system bus in PXI, and LabVIEW graphical system design software to address the business and technology challenges of high-frequency test and measurement. Read the white paper.
VPX for High-Performance Avionic Computers
Traditional high-performance computing platforms are limited by the connection bandwidth and latency between the multiple computing elements needed to achieve the performance targets. For the embedded market, the difficulty is compounded by the demanding environmental requirements. The VPX standard resolves this limitation with a large number of high-throughput point-to-point connections between the processing elements in a rugged mechanical structure.
Upcoming Events
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CST Workshop Series 2013 - EDA & EMC
Dave & Buster’s Restaurant and Arcade 71 Fortune Drive, Irvine, CA 7270555 USA June 20, 2013
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SEMICON West 2013
San Francisco, CA July 9-11, 2013
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RTECC Real-Time and Embedded Computing Conference
Washington DC July 23rd, 2013
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26th IEEE International SoC Conference
Erlangen, Germany September 4 - 6, 2013
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IPC Conference on Component Technology: Closing the Gap in the Chip to PCB Process
Hilton Phoenix Chandler, Chandler, AZ USA September 10 - 12, 2013
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European Microwave Week
Nuremberg, Germany October 6-11, 2013
EECatalog Tech Videos
RTL Signoff turns competitive
In our fourth interview this week at the Design Automation Conference in Austin, Texas, EiC John Blyler of Chip Design talks with Mike Gianfagna, Vice President of Corporate Marketing at Atrenta, about the growing competition and advances in RTL Signoff.
Code integration facilitates chip innovation
Chip Design's John Blyler interviews Cristian Amitroaie, CEO of AMIQ (http://www.amiq.ro) on the importance of code integration and the Eclipse platform At the Design Automation Conference in Austin, Texas.
Collaboration is the key to chip innovation
In our third interview at the Design Automation Conference in Austin, Texas, John Blyler of Chip Design Magazine talks with Dennis Bibeau of Infotech about the importance of collaboration across all disciplines in achieving innovative chip design.
Innovating with Statistical Analysis
In our first interview at the Design Automation Conference in Austin, Texas, John Blyler talks with Zhihong Lu of Proplus (http://www.proplussolutions.com/en/contact/) about the problems and potential of innovation in chip design through statistical analysis.
GigOptix-40G DQPSK Demonstration
GigOptix demonstrates 40G DQPSK with revolutionary TFPS polymer modulator
Cost-Effective Millimeter Signal Analysis Approaches | Agilent Technologies
This video was provided by IEEE.tv's coverage of IMS 2012 in Montreal. Material was created by Ben Zarlingo and presented by Bruce Erickson of Agilent Technologies. http://www.agilent.com/find/sa
SDC Management and Verification: What's Missing?
Sarath Kirihennedige, Sr. Manager Product Engineering at Real Intent, speaks with Graham Bell about how design constraints (SDC) are currently developed, what are the problems with the current approach and what a complete Constraints management and verification solutions looks like.
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PLL and DLL Hard Macros
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