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Many aspects of a PCB’s performance are determined during detailed design. Thermal issues with the PCB design are largely ‘locked in’ during the component (i.e. chip package)
Recently, physics-based reliability prediction has related electronic assembly failure rates to the rate and magnitude of temperature change over an operational cycle, both of which are influenced by steady-state operating temperature. Whether the intention is to increase reliability, or improve performance, accurate prediction of component temperatures helps meet design goals.
A natural focus when designing electronics products are, well the electronics. The electronics itself however, needs to work within some kind of enclosure, and must be designed with the enclosure in mind. Cooling is a system issue, which is why we advocate a top-down approach, starting at the enclosure level.
Data center power load (and therefore heat dissipation) footprints continue to rise in response to growing demand for information storage and transfer. Cooling constitutes a major cost in the operation of a data center which has led to increased focus on minimizing energy use in data centers.
Reduce Metastability by Using a User Grey Cell™ Methodology for IP and FPGA Clock Domain Crossing Analysis
This paper introduces a novel technique for Intellectual Property (IP) and FPGA clock domain crossing (CDC) analysis using Blue Pearl’s User Grey Cell™ methodology rather than the traditional Black Box methodology.
ASIC and & FPGAs have many false paths that implementation tools attempt to optimize to make timing goals. Adding false path constraints frees up the synthesis tool to work only on necessary paths. Blue Pearl automates false path generation that can be run after design changes
Packet processor design teams face increasingly difficult challenges as they seek to provide their network equipment manufacturers with state-of-the-art devices. The interrelated system-level trade-offs include performance, pin count, and area, and are all ultimately limited by power consumption considerations. To successfully compete, network chip vendors must consider end-to-end solutions for system architects and developers. In turn, as OEMs introduce multi-terabit systems, they must aggregate multiple 100 Gbps ports on each line card or risk falling behind the performance curve.
EECatalog Tech Videos
Intellitech's CEO CJ Clark explains why the latest JTAG update brings much needed capabilities to IP providers and IC developers alike.
Motion sensing applications with mm wave technology at Imec is the topic of this interview between Liesbet Van der Perre, Imec Program Director of Wireless Communication, and John Blyler, VP and CCO at Extension Media.
Wally Rhines, Chairman and CEO of Mentor Graphics, talks about Moore's Law in light of the Learning Curve; 28nm as the golden node; critical need for IoT innovations; and why systems engineering often fails.
In our third interview at the Design Automation Conference in Austin, Texas, John Blyler of Chip Design Magazine talks with Dennis Bibeau of Infotech about the importance of collaboration across all disciplines in achieving innovative chip design.
Chip Design's John Blyler interviews Cristian Amitroaie, CEO of AMIQ (http://www.amiq.ro) on the importance of code integration and the Eclipse platform At the Design Automation Conference in Austin, Texas.
In our first interview at the Design Automation Conference in Austin, Texas, John Blyler talks with Zhihong Lu of Proplus (http://www.proplussolutions.com/en/contact/) about the problems and potential of innovation in chip design through statistical analysis.
In our fourth interview this week at the Design Automation Conference in Austin, Texas, EiC John Blyler of Chip Design talks with Mike Gianfagna, Vice President of Corporate Marketing at Atrenta, about the growing competition and advances in RTL Signoff.