Real Intent Technologist Presents Power-related Paper and Tutorial at ISQED 2013 Symposium

Real Intent, Inc., participating with Intel Corp. and University of Texas Austin, presents a paper and a tutorial at this year’s International Symposium on Quality Electronic Design (ISQED). ISQED is the premier interdisciplinary and multidisciplinary Electronic Design conference that bridges the gap among electronic/semiconductor ecosystem members providing electronic design tools, integrated circuit technologies, and semiconductor technology, packaging, assembly & test to achieve design quality.

Dr. Vinod Viswanath, Senior Member Technical Staff at Real Intent, along with experts from Intel Corp. and University of Texas Austin

Present a joint paper, On a Rewriting Strategy for Dynamically Managing Power Constraints and Power Dissipation in SoCs (systems-on-a-chip), covering a novel and highly automated technique for dynamic system-level power management of SoC designs. It includes a formal system to represent power constraints and power intent as rules, and a term rewriting systems-based rule that rewrites the engine as a dynamic power manager. Two fundamental building blocks provide a common platform for seamless cooperation between hardware and software constraints to achieve maximum platform power optimization dynamically during execution, as demonstrated in multiple contexts on an SoC design of the state-of-the-art next-generation Intel smartphone platform.

Vinod also presents a tutorial, with experts from Intel India, covering a trend to maximize power optimization: Holistic Power Management: The Future of Handhelds and other Low Power Devices. It delves into power efficiency as a growing concern for all aspects of computing systems – from very small, highly integrated SoC-based handheld devices to larger systems including servers and many-core high-performance computing systems. It also addresses the challenges of a unified specification of power intent across all design abstraction levels; power optimization and holistic power management techniques; and the challenges of verifying such a system. Real life examples from Intel’s experience in designing some of its latest handheld devices are used.

Tutorial: Monday, Mar. 4, 2013, 4:50-6 p.m.
Paper: Tuesday, Mar. 5, 2013, 2:30 p.m., at
Techmart – 5201 Great America Parkway, Suite 122, Santa Clara, Calif. 95054

About Real Intent
Companies worldwide rely on Real Intent’s electronic design automation (EDA) software to accelerate early functional verification and advanced sign-off of electronic designs. Real Intent’s comprehensive clock domain crossing (CDC) verification, advanced register transfer level (RTL) analysis and sign-off solutions eliminate complex failure modes of SoCs, and lead the market in performance, capacity, accuracy and completeness. Please visit for more information.

Contact Information

Real Intent

990 Almanor Ave
Suite 220
Sunnyvale,, CA , 94070

tele: 408-830-0700
fax: 408-737-1962

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