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Calypto Participates in Technical Session at DATE 2013: Detecting Isomorphisms in Logic Design

At DATE 2013, Calypto® Design Systems, Inc., the leader in electronic system level (ESL) hardware design and register transfer level (RTL) power optimization, will present in a technical session on an innovative approach to detecting isomorphisms in logic design and formal verification. This work is based on collaboration between Calypto and UC Berkeley that is aimed at simplifying formal analysis of circuit logic. Calypto technologies let designers create high-quality, low power ASIC and FPGA hardware products. Calypto’s three product families (PowerPro®, Catapult® and SLEC®) offer customers solutions ranging from RTL power reduction to C++/ SystemC high-level synthesis.

WHAT:

 

Technical Session 649: A Semi-Canonical Form for Sequential AIGS

 

SPEAKERS:

Alan Mishchenko, Niklas Een and Robert Brayton – University of California, Berkeley, US

Michael Case, Pankaj Chauhan and Nikhil Sharma – Calypto Design Systems

 

WHERE:

Alpexpo Espace Alpes Congres

Grenoble, France
 

WHEN:

Wednesday, March 20, 2013

1430 – 1600

Room, Belle-Etoile

This presentation describes a way to use simulation to quickly identify isomorphisms. By repeatedly simulating the netlist, unique signatures for each gate are derived. If two netlists, simulated separately, have the same signatures then these netlists are isomorphic. Any results computed on one netlist can be safely applied to the second netlist, leading to dramatic speedups overall.

The results presented in this session focus on sequential equivalence checking, and for this purpose, isomorphic proof obligations are identified. If two proof obligations are isomorphic, then the tool only needs to derive a formal proof for one of the obligations, thus reducing the total number of proof obligations that need to be considered. In this presentation, we look at a variety of industrial equivalence checking testcases and demonstrate that:

  • This simulation-based approach can identify the isomorphic proof obligations in mere seconds.
  • On average, the number of proof obligations is reduced by 61%.
  • The time needed to prove the proof obligations is reduced by 60%.

About Calypto’s Products

Catapult high-level synthesis, SLEC® (Sequential Logic Equivalence Checking) and PowerPro platforms are used to design, verify and optimize complex SoC and FPGA designs by seven out of the top ten semiconductor companies and over 100 leading consumer electronics companies worldwide. Calypto’s products enable engineers to dramatically improve design quality and reduce power consumption of their SoC while significantly reducing overall design and verification time.

About Calypto

Calypto® Design Systems, Inc. is the leader in ESL hardware design and RTL power optimization. Calypto, whose customers include Fortune 500 companies worldwide, is a member of the ARM Connected Community, Cadence Connections program, the IEEE‐SA, Synopsys SystemVerilog Catalyst Program, the Mentor Graphics OpenDoor program, Si2 and is an active participant in the Power Forward Initiative. Calypto has offices in Europe, India, Japan and North America.

Catapult, Calypto, PowerPro and SLEC are registered trademarks of Calypto Design Systems Inc. All other trademarks are property of their respective owners.

Contact Information

Calypto Design Systems

1731 Technology Drive
Suite 340
San Jose, CA, 95110
USA

tele: 408.477.8166
fax: 408.850.2321
info@calypto.com
www.calypto.com

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