PLL and DLL Hard Macros
True Circuits’ complete family of standardized, silicon-proven, low-jitter PLL and DLL hard macros spans nearly all performance points and features typically requested by ASIC, FPGA and SoC designers. Using robust state-of-the-art circuits, a methodical and proven design strategy, and close associations with the world’s leading fabs, IDMs and design services companies, True Circuits is able to quickly and reliably create new and innovative designs in a variety of advanced process technologies.
True Circuits’ clock generator, spread spectrum, low bandwidth, deskew and general purpose PLLs support wide operating frequency ranges and multiplication factors over which they deliver optimal jitter performance, avoiding the cost and complexity of licensing multiple point-solution PLLs from other vendors.
The clock generator PLL supports fractional-N frequency multiplication and is available with multi-phase outputs. The spread spectrum PLL allows precise adjustment of spreading rate and depth, with 4 bits of precise fractional-N control, optional multi-phase outputs, and very low long-term jitter. The general purpose PLL is ideal for low power, area sensitive and low cost applications.
True Circuits’ multi-slave DLL delays a set of signals by precise and adjustable fractions of a reference clock cycle independent of voltage and temperature. The multi-phase DLL generates precise multi-phase clocks. These DLLs have flexible form factors for easier integration and are ideal for high-speed DDR and other interface applications.
Features & Benefits
- Clock Generator, Spread Spectrum, Low Bandwidth and Deskew PLLs
- General Purpose PLLs
- Multi Slave and Multi Phase DLLs
- Support the latest ARM processor, DDR, SerDes and audio/video standards
- Optimized for size, power and performance
- Low-jitter and very process tolerant
- Large multiplication factors (1-4096)
- Wide output frequency ranges
- Pin Programmable
- Customization available upon request
See us at the TSMC Technology Symposiums
April 9, San Jose, CA
April 16, Austin, TX
- Available in TSMC, GLOBALFOUNDRIES, UMC and Common Platform processes from 180nm to 20nm
- GDSII and LVS Spice netlists
- Behavioral, synthesis and LEF models
- Extensive user documentation
- Integration support to ensure successful tape outs
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