Si2’s OpenPDK Coalition Releases ESD Design Flow Methodology
The Silicon Integration Initiative (Si2) announced today that the ESD (Electro-Static Discharge) Working Group of the OpenPDK Coalition has released an ESD Protection Design Flow Methodology “best practices” document for industry-wide adoption in order to promote a more consistent treatment of this important aspect of integrated circuit (IC) design. At advanced process nodes, it becomes increasingly critical to adhere to strict ESD design guidelines, because inadequate ESD protection can reduce effective yield and thus increase overall costs. This document provides comprehensive guidelines for incorporating ESD protection into IC design flows. The ESD Working Group that developed this document included representatives from IBM, Intel, GlobalFoundries, NXP, Samsung, and STMicroelectronics.
The design of ESD (Electro-Static Discharge) protection devices in an IC should be evaluated and verified at all stages of a standard circuit design flow starting from the Cell Schematic level and ending at the Full Chip Layout level. A comprehensive set of ESD checks should be verified using appropriate tools at each of these levels to ensure that the integrated circuit has robust ESD protection. The released document describes the ESD design flow, the various checking tools that are used at each level and the requirements for each of these tools. It is available to the industry at: http://www.si2.org/openeda.si2.org/project/showfiles.php?group_id=82&release_id=558
The ESD design flow document examines such items as: Schematic Level Checking (Cell & Full Chip Level), Layout Level Checking, Power Bus Resistance Extraction Tool, Floor Planning Level Checking, Evaluation Expectations, and Tool Infrastructure.
"For technology scaling at the 130nm node and below, first-time-right product ESD protection results have become important using classical verification methodologies. The complete ESD design flow and verification as presented by the Si2 ESD Working Group starting from cell level ESD schematic design and ending at full chip layout verification is essential for the semiconductor industry to achieve successful ESD results in leading edge semiconductor technologies.” Robert Gauthier – Technical VP of Operations, ESD Association.
The goal of the OpenPDK Coalition is to define a set of open standards to define a PDK structure that will be as portable across foundries and as agnostic to EDA tools as possible. The OpenPDK from Si2 will enable greater efficiency in PDK development, verification and delivery and will provide equivalent support to all foundries, all EDA tool vendors, all IP providers, and all end users. The OpenPDK project aims to support all process nodes including high-voltage analog processes. For more information, see: http://www.si2.org/?page=1118
Membership in Si2 projects is open to all interested parties across the semiconductor supply chain. For more information see: http://www.si2.org/?page=1137
OpenPDK Member Companies
AnaGlobe Technology, Cadence Design Systems (NASDAQ: CDNS), GLOBALFOUNDRIES, IBM (NYSE: IBM), Intel (NASDAQ: INTC), Mentor Graphics (NASDAQ: MENT), NXP (NASDAQ: NXPI), Samsung Electronics (KSE: 005930), Silvaco, and STMicroelectronics (NYSE: STM).
Si2 is the largest organization of industry-leading semiconductor, systems, EDA and manufacturing companies focused on the development and adoption of standards to improve the way integrated circuits are designed and manufactured, in order to speed time-to market, reduce costs, and meet the challenges of sub-micron design. Now in its 25th year, Si2 is uniquely positioned to enable timely collaboration through dedicated staff and a strong implementation focus driven by its member companies. Si2 represents over 80 companies involved in all parts of the silicon supply chain throughout the world. See www.si2.org.