USB 3.0 SSIC: Low-Power Interconnect for Mobile Consumer Applications
Using an existing USB 3.0 software stack with the low-power capabilities of the MIPI M-PHY lets designers meet the increasing performance and battery life requirements of mobile or low-power electronics
While 6 billion people know about USB on the outside of smartphones, cameras, and laptops, only product designers are familiar with how USB is used inside of these products. In laptops, for example, the touchpad, webcam, and broadband modem often use standard USB parts—consuming standard USB power—internally. For example, a USB 3.0 camera will use a USB 3.0 PHY connection (with a cable) to a USB 3.0 PHY on the circuit board (internally). The camera maker can easily implement standard USB 3.0 drivers for both the embedded camera on the PCB system on chip (SoC) and the external camera. The disadvantage to the designer is that using two USB 3.0 PHYs drain the battery because they double the required power over the tiny distance inside the chassis.
Improving Speed, Power and Area with USB 3.0 SSIC and MIPI M-PHY
The USB Implementers Forum (USB-IF) introduced USB 3.0 in 2008 to increase speed and throughput, and soon after they introduced the SuperSpeed Inter-Chip (SSIC) standard for on-PCB communication to reduce power consumption. Less power is required when transmission distances shrink from meters to centimeters or millimeters, as they do inside mobile devices. SSIC uses the MIPI M-PHY to enable products implementing the standard to use as little as 20 percent of the power consumed by a USB 3.0 PHY.
To promote rapid adoption of SSIC, the USB-IF aligned SSIC with the MIPI Alliance’s gigabit-speed, on-PCB, chip-to-chip PHY called the MIPI M-PHY. M-PHYs consume lower power and offer greater flexibility than USB 3.0 PHYs. M-PHYs can come in three speeds, called Gears. Gear1 operates at 1.25 or 1.45 Gbps, Gear2 at 2.5 to 2.9 Gbps, and Gear3 up to 5.8 Gbps. In addition, M-PHYs can have 1, 2, or 4 lanes. Each lane has x pins, so two lanes have 2x pins and four lanes have 4x pins. These lane configurations offer flexibility to run either in multiple parallel lanes at slower clock speeds to save power, or to run at faster speeds but consume fewer pins. Since many SoCs are pin and/or pad limited, designers often choose the faster Gear3 standard to save pins. A one-lane MIPI M-PHY has 16 pins. On the other hand, a standard USB 3.0 PHY has at least 15 pins including USB 2.0 D+ and D-; USB 3.0 Tx+, Tx- Rx+, Rx-, power, and ground pins.
The MIPI Alliance and USB-IF worked together to standardize the interface between USB 3.0 controllers and MIPI M-PHYs. According to the standard, the USB 3.0 controller uses a standard PIPE interface, which is the same interface for the USB 3.0 path to a USB 3.0 PHY. While the PIPE interface is preserved, the system still needs an interface to a standard M-PHY. The M-PHY v2.0 specification defines the SSIC interface to the M-PHY as the Reference M-PHY Module Interface (RMMI). The logic bridge between the USB 3.0 controller and the M-PHY is called the PHY Adapter. While it sounds simple, the PHY Adaptor is complex as it must synthesize and operate with the controller and the PHY. It must support USB 3.0 power savings modes (U1, U2, U3, and U4) while supporting 1, 2, or 4 lanes and/or Gear1, 2, or 3 speeds.
|Figure 1: Standardized SSIC interface between USB 3.0 and MIPI M-PHY|
Using High-Speed Gear3 M-PHY with USB 3.0
The MIPI M-PHY v3.0 specification defines low-power implementation for chip-to-chip connectivity, including several high-speed gears that match the burst speed needed by a given application, as well as low-speed pulse width modulation gears that are used mostly for control. The specification also defines a variety of low-power modes that the link can utilize to enter and exit during long or brief idle times and rapidly get back to burst mode.
A MIPI M-PHY is about 50 percent smaller than a USB 3.0 PHY and consumes significantly less power, especially in Gear1, 1 lane operation. In this configuration, a MIPI M-PHY consumes only 20 percent of the power of a USB 3.0 PHY. For two devices connected on PCB, this 80 percent power reduction during active operation at the system level is significant for portable devices. Part of this power savings is due to the smaller PHY, and part is because the Gear1, 1 lane M-PHY data rate is only 1.25 or 1.45 Gbps. As a USB 3.0 PHY always operates at 5 Gbps, the M-PHY allows for the lower data rate and power savings.
The high-speed MIPI M-PHY, working in conjunction with USB 3.0 SSIC, is tailored for mobile applications and is becoming a popular physical layer solution. With up to 5824 Mbps bandwidth, the High Speed Gear3 serialization speed meets devices’ high bandwidth requirements. The M-PHY is designed to accommodate the intermittent nature of inter-chip communications and employs burst operation to toggle between data transmission and power saving states, effectively reducing power consumption.
Multiplexing with M-PHY
In most designs in the near future, a smartphone/tablet application processor SoC with a fully integrated USB 3.0 SSIC controller and M-PHY will connect on the PCB to a modem or WiFi SoC. The WiFi SoC also has an M-PHY and USB 3.0 controller. A second USB 3.0 controller and USB 3.0 PHY may be used for external USB connections. On an applications processor, this may be an external port for connecting to a USB 3.0 flash drive. In addition, the single M-PHY can be multiplexed with other MIPI functions.
In Figure 2, a single M-PHY is used with an LLI controller to allow the baseband of a wireless device to use the RAM for the applications processor. By multiplexing a single PHY with two digital controllers, designers save the area of an extra M-PHY, as long as only one digital controller is working at any one time. A MIPI M-PHY may also be MUXed with a PCIe controller to implement M-PCIe.
|Figure 2: Example of using a single M-PHY with two controllers (USB 3.0 and LLI)|
Using a MIPI M-PHY with SSIC controllers can result in up to an 80 percent power savings over USB 3.0 PHYs. The SSIC standard improves power efficiency while reducing area and maintaining throughput and preserving SSIC software compatibility. This makes SSIC attractive to designers of smartphones, tablets, and the wireless products they connect to, as SSIC offers bandwidth and power advantages in these highly competitive markets.
A fully integrated USB 3.0 SSIC controller and M-PHY enables low-power, efficient connectivity on a PCB between a smartphone/tablet application processor to a modem or WiFi SoC. Using an existing USB 3.0 software stack with the low-power capabilities of the MIPI M-PHY enables designers to meet the increasing performance and battery life requirements of mobile or low power electronics.
Eric Huang worked on USB at the beginning in 1995 with the world’s first BIOS that supported USB keyboards and mice while at Award Software. After a departure into embedded systems software for real-time operating systems, Eric returned to USB cores and software at inSilicon, the leading supplier of USB IP in the world. inSilicon was acquired by Synopsys in 2002. Eric served as Chairman of the USB On-The-Go Working Group for the USB Implementers Forum from 2004-2006.
Eric Huang received an M.B.A. from Santa Clara University and an M.S. in Engineering from University of California Irvine, and a B.S. in Engineering from the University of Minnesota. He is a licensed Professional Engineer in Civil Engineering in the State of California.
Hezi Saar serves as a staff product marketing manager at Synopsys and is responsible for its DesignWare MIPI controller and PHY IP product line. He brings more than 15 years of experience in the semiconductor and electronics industries in embedded systems. Prior to joining Synopsys, from 2004 to 2009, Saar served as senior product marketing manager leading Actel’s Flash field-programmable-gate-array (FPGA) product lines. Previously, he served as a product marketing manager at ISD/Winbond and as a senior design engineer at RAD Data Communications. Saar holds a bachelor of science degree from Tel Aviv University in computer science and economics and an MBA from Columbia Southern University.