Disruptive New Serial-Interface; Intelligent Memory Architecture Jumps 100/400GbE Performance Wall

Packet processor design teams face increasingly difficult challenges as they seek to provide their network equipment manufacturers with state-of-the-art devices. The interrelated system-level trade-offs include performance, pin count, and area, and are all ultimately limited by power consumption considerations. To successfully compete, network chip vendors must consider end-to-end solutions for system architects and developers. In turn, as OEMs introduce multi-terabit systems, they must aggregate multiple 100 Gbps ports on each line card or risk falling behind the performance curve.

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MoSys, Inc.

3301 Olcott Street
Santa Clara, CA, 95054

tele: 408-418-7500
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