Overcoming Challenges in 3D Architecture Memory Production
RRAM is the only alternative to NAND that will be viable over the next few years based on cost, manufacturability and gains in overall system performance. Current NAND technology has hit its scaling limits at the 1Y node, and 3D-NAND is the next alternative to NAND, enabling continuous cost reduction and scaling. However, the performance of the cells in 3D-NAND are inferior to NAND, which increases system complexity. The controller complexity is also increased because of the poor on/off ratios with 3D-NAND similar to planar NAND cells.
The introduction of any new memory technology starts with a phased approach that involves proving the cell performance, array performance and also the ability to provide solutions for different markets. The materials and structures in NAND flash were all proven or developed with NOR flash growth. There are limited memory cell technologies that can provide that going forward, either due to scaling, stacking or architecture limits. Integrating a resistive memory element in backend metal layers provides this opportunity for current generation memories. (Figure 1) below compares a logic CMOS with an embedded memory that is closer to gate level with an embedded memory that is integrated in the backend. Backend integration provides multiple advantages including smaller die size, easier introduction of new elements to volume manufacturing fabs and lower cost per bit. This also enables porting the same memory cells for storage nodes.
|Figure 1: Schematic showing Logic CMOS on left vs. e-flash vs. Resistive Memory. The front end vs. backend integration of the memory element  and the impact towards die size  are highlighted.|
The cost increase for embedding the resistive memory element is less than four percent compared to a logic circuit with no memory, and is at least 12 percent less compared to current embedded flash memories. There is a one-time capital cost for setting up a dedicated toolset for early introduction of new elements (approximately $7 Million for a 3000 wpm line) which scales with the wafer output. The overall cost of manufacturing is still ~12 percent cheaper when normalizing the volume of wafers processed over time with the resistive memory for data or storage applications.
3D-NAND architecture involves deep trench etches to simultaneously make contacts to cells across 16 to 32 alternating conducting and insulating layers. This enables stacked cells, smaller die size and a lower cost. However, the yield impact due to this architecture increases the cost. The trenches also have to be vertical. Any deviation from vertical trenches increases the die size and increases the cost. NAND and 3D-NAND also require gate dielectrics that support a 20+ Volt operation. A schematic comparison of planar NAND, 3D-NAND and a Crossbar RRAM are shown below (Figure 2).
A resistive memory like Crossbar’s RRAM is integrated in alternate stacks between wiring layers. Each layer is independent of the previous layer with respect to defects, and therefore has a reduced impact on yield. With the ability to do Multi-Level Cells (MLC’s), Crossbar requires fewer stacked layers for the same memory density. In addition, Crossbar RRAM is scalable down to sub-10nm, is backend compatible and simplifies the overall system performance with features such as byte alterability and a significantly lower Bit Error Rate (BER).
Given the advantages of Resistive memory, it is an obvious choice to replace 3D-NAND. Next steps will be to use a phased introduction approach for RRAM in volume fabs for code applications first, followed by data storage applications.
Sundar Narayanan, PH.D., VP of Technology, Crossbar-Inc.
Dr. Sundar Narayanan has been vice president of Technology at Crossbar since October 2012 and oversees the development of the company’ Resistive Memory technology. He brings to Crossbar over 15 years of industry experience in technology development specializing in prototyping, commercialization, technology transfer, yield enhancement and Low Rate Initial Production.
In 2011 as head of Engineering at SVTC Technologies, Dr. Narayanan lead a team of 70 engineers in the company’s San Jose and Austin facilities, developing diverse technologies that enabled the transformation of great ideas to revolutionary products for customers. He created and organized the technology development process taking ideas from prototypes, through the validated processes, and to Specialty Production across multiple device platforms in memories, such as CMOS and NVMs (including SONOS, PCM, CBRAM, MRAM), MEMS, BioMEMS, Photonics and Energy.
Dr. Narayanan also ran the San Jose Fabrication facility as the Fab director for two years, improving operational and engineering efficiency to enable the transition from a captive fab to one where R&D and LRIP are done in parallel.
Prior to SVTC, he spent a decade at Cypress Semiconductor working on Process and Device Integration. He has 14 issued U.S. and international patents and over 20 publications in journals and conference proceedings.
Dr. Narayanan has a Ph.D. from Drexel University, was a Visiting Scholar and Post-Doctoral Researcher at Rensselaer Polytechnic Institute in Troy, New York, and is a Six Sigma Green Belt from ASQ.