The truth about knowing your False Paths

ASIC and & FPGAs have many false paths that implementation tools attempt to optimize to make timing goals. Adding false path constraints frees up the synthesis tool to work only on necessary paths. Blue Pearl automates false path generation that can be run after design changes



Before you download the white paper, please sign our guest book

Please register or log in to view this white paper

Login

If you've already created an account with us, please login here



Lost your password?

Register

User Information




Contact Information

Blue Pearl Software

4677 Old Ironsides Drive
Suite 430
Santa Clara, CA, 95054
USA

tele: 408.961.0121 x302
bill@bluepearlsoftware.com
www.bluepearlsoftware.com