The truth about knowing your False Paths

ASIC and & FPGAs have many false paths that implementation tools attempt to optimize to make timing goals. Adding false path constraints frees up the synthesis tool to work only on necessary paths. Blue Pearl automates false path generation that can be run after design changes

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Blue Pearl Software

4677 Old Ironsides Drive
Suite 430
Santa Clara, CA, 95054

tele: 408.961.0121 x302