Speed design verification by developing cleaner SV/UVM code

There are many challenges when designing ICs that contain tens to hundreds of millions of gates and it won’t get any easier as next-generation designs cross the gigagate threshold. With such complex designs, it’s rare that the design will be error-free on the first try, and that means additional time and resources must be spent to troubleshoot and repair the circuit to make it production worthy.

Figure 1: Separation of FPGA and End Application Design Paths.

To improve the odds of getting working silicon on the first attempt, design verification tools have helped designers analyze the circuits to find potential flaws. Over the past decade the tools have made major strides, but evaluating the results often requires the designers to know what they are looking for. That’s where a novel software tool – DVinsight—developed by Agnisys Inc., of Lowell, Mass. can come to the aid of designers explained Anupam Bakshi, the company’s CEO. The tool allows designers to create SV/UVM code in a simple way that is correct by construction and it can be a powerful tool in the toolbox for both expert and novice verification engineers.

The DVinsight tool from Agnisys can almost read the designer’s mind and create bug-free verification code.

According to Bakshi, the verification code created using Dvinsight requires very little debugging since it prevents bugs from being written into the code in the first place. That accelerates the design verification process and leads to higher-quality code in less time. The tool was designed to “understand” the engineer’s intentions and will point to issues before they become big and lead to major problems downstream. Additionally, the tools can provide guidance to the user and includes an advance warning system that can catch design flaws early. The tool can also help the user visualize the code and can thus become an indispensable companion for serious UVM code developers.

Like a detective evaluating clues from a case, the DVinsight software evaluates design files and produces an analysis of circuit issues that design and verification engineers can use to further improve their designs. This tool adds more intelligent analysis to the designer’s repertoire by allowing designers to specify functionality in the tool and then automatically generates the verification code. Plus, the basic tool will be offered at no cost; however for a small fee, some advanced features will be made available. The company will officially launch the tool at next month’s Design Automation Conference in San Francisco.

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