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Agnisys

IDesignSpec™

IDesignSpec™ is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically generate all possible views and code from it for Design, Design Verification, Software and Documentation. An extensive list of outputs is possible including UVM, OVM, RALF, SystemRDL, IP-XACT and more. Other user-defined outputs can be created using Tcl or XSLT scripts adding to the solution’s extensibility. IDesignSpec is patented technology that improves engineer’s productivity and design quality while enabling the many SOC or FPGA project specification changes to be quickly and accurately migrate to each project team stakeholder’s code and documentation.

FEATURES & BENEFITS

  • Automatically verify all addressable registers in the design to eliminate errors before they can impact project schedules
  • Create synthesizable code for registers for the design ensuring correct by construction implementation of the SoC or FPGA
  • Accelerate Device Driver, Firmware and Application Software by automating header file generation – MISRA-C compatible
  • Ensure documentation for customers and Tech-Pubs is accurate and kept synchronized with SoC design and verification
  • Built-in support all major (parallel) register busses: AMBA AHB, APB, AXI, OCP-IP, Avalon, with simple custom register support

Contact Information

Agnisys

1255 Middlesex St. Unit I
Lowell, MA, 01851
USA

tele: 1855-VERIFYY
fax: 1855-VERIFYY
http://www.agnisys.com/

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