New Agreements Boost IEEE P1687 IJTAG Standard

Two new agreements, announced at this year’s International Test Conference (ITC), held October 21-23 in Seattle, Washington, will help boost the use of the IEEE P1687 “IJTAG” standard. ASSET InterTech and Mentor Graphics announced “seamless interoperability” for the IEEE P1687 Internal JTAG (IJTAG) embedded instrumentation standard. Also at ITC, SiliconAid Solutions announced support of IEEE P1687 and IEEE 1149.1-2013 Standards through a partnership with Ridgetop Group.

The industry developed IEEE P1687 (IJTAG) to manage the complex requirements of testing a heterogeneous set of embedded IP. It standardizes a language for describing the IP interface and how IPs are connected to each other. It also introduces a language that defines how patterns that operate or test the IP are to be described. IEEE P1687 draws a clear line between what must be covered by the standard and what is better left to the ingenuity of the tool developers.

One of the first products to bring IEEE P1687 to life is Mentor Graphics’ Tessent IJTAG, which provides automation and features beyond the basic implementation of the languages of IEEE P1687. It simplifies the process of connecting any number of IEEE P1687 compliant IP blocks into an integrated, hierarchical network and to communicate commands to the blocks from a single top level access point. It provides a flow in which the user does not need to know the ins-and-outs of IEEE P1687, but can leave it up to Tessent IJTAG to find the best possible solution for his IEEE P1687 compliant design.


What was announced at ITC was interoperability between ASSET InterTech and Mentor Graphic Tessent IJTAG, which empowers two-way validation flow between chips and boards. It will allow engineers to accurately debug and isolate issues in either a complex system-on-a-chip (SoC) or on the circuit board where the chip has been deployed. ASSET and Mentor demonstrated IJTAG interoperability at ITC.

IJTAG resources, including embedded instruments and a network connecting them, are inserted into a chip with Mentor’s Tessent IJTAG solution. These instruments then allow engineers to verify and characterize the functionality and performance of the SoC at the chip level. When deployed on a circuit board, ASSET’s ScanWorks tool will be able to provide a debug loop by accessing IJTAG resources to isolate problems in both the SoC and the circuit board. Issues found at the chip level can be corrected before additional devices are fabricated.

“This two-way debug feedback between chip and board eliminates any doubt about whether the faulty behavior is in the chip or on the board,” said Al Crouch, vice chairman of the IEEE P1687 IJTAG working group and a chief technologist for ASSET. “Of course, conformance to the IEEE P1687 standard is critical to the interoperability between our ScanWorks tool and Mentor’s Tessent IJTAG solution. In my opinion, IJTAG will take a major step toward approval soon and once that happens, momentum will quickly increase for full industry adoption.”

“The complexity of today’s SoCs and the growing number of IP blocks integrated into these designs are making IJTAG a necessity if the industry is going to maintain its rapid pace of new product introductions,” said Stephen Pateras, Product Marketing Director at Mentor Graphics. “Aligning Tessent IJTAG with ASSET’s ScanWorks is a big step toward enabling our customers to fully capitalize on the potential of the IJTAG standard.”

A series of IJTAG workshops is currently being planned by ASSET and Mentor for the spring of 2015. Attendance at one half-day session is priced at $295. Following the morning workshop, a limited number of private consultations will be available with the experts who will be teaching the workshop.

SiliconAid and Ridgetop

Also at ITC, SiliconAid Solutions, Inc., and Ridgetop Group., announced jointly that they have continued and expanded their partnership to enable support for the evolving industrial testability standards. Together they have developed a system to embed Ridgetop Group’s SJ BIST™ board-level interconnection reliability monitor leveraging IEEE P1687 and IEEE 1149.1-2013 for intellectual property (IP). SJ BIST is a patented test IP product that detects interconnect faults between electronic devices, such as between ICs, FPGAs, SoCs and PCBs.

Ridgetop and SiliconAid applied SiliconAid’s IEEE 1149.1-2013 and P1687 tool flows to develop compliant access to SJ BIST IP. Ridgetop continues to be a partner/customer to test and verify the SiliconAid IEEE 1149.1-2013 and P1687 flows. These adjusted implementations leverage enhanced automation, reuse, and debug capabilities of embedded chip instruments. In the past, a significant manual effort has been required to verify that embedded instruments were integrated and verified correctly in the customer design. Procedural Description Language (PDL) test pattern generation also had to be handled by the IP integrator. Using SiliconAid’s new flow, a custom testbench can be generated automatically for every design in which the IP is used. Chip-level automated test equipment (ATE) patterns can also be generated automatically.

According to Andrew Levy, Ridgetop’s VP of Business Development, “SJ BIST offers a solution for detecting troublesome intermittencies. We have worked with SiliconAid to take Ridgetop’s SJ BIST Test IP Core through their P1687 IJTAG and boundary scan flows. Now that we have developed and demonstrated the ability to convert legacy patterns to PDL patterns that can be applied with these interface, our customers will enjoy even faster and more flexible deployment of SJ BIST to meet their needs for highly reliable boards and systems.”

Jim Johnson, SiliconAid President and CTO, added, “We believe all IP providers will soon be delivering with support for both P1687 and 1149.1-2013 to enable IP reuse. The Plug and Play approach used by these new standards is a perfect fit for an IP provider like Ridgetop to improve quality and help the chip integrators. Utilizing these new standards will reduce the cost of integration, verification, and test pattern generation for the SOC companies using the IP. We support both of these two new standards and have a robust suite of tools to meet your needs for IP developers, SOC integrators, verification, manufacturing test, debug, and more.”

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