print

“Sneak Path” Breakthrough Heralds Arrival Of Ultra-High Density Resistive Memory

As floating-gate flash memory technologies used in the majority of products on the market today quickly approach the limits of their ability to scale to higher densities, it has become widely recognized that a new non-volatile memory technology is needed to replace them. Resistive random-access memory (RRAM) is widely hailed as the “most likely to succeed” in the race to replace today’s flash memory with a new, more scalable, higher-capacity, higher-performance and more reliable non-volatile memory. While many companies are actively pursuing RRAM technologies, however, the road to creating commercially viable RRAM products has not been easy.

One of the greatest challenges facing developers in achieving ultra-high density RRAM (>1Tb) has been overcoming the leakage (sneak) current problem in crossbar arrays that interferes with the reliable reading of data from individual memory cells and increases power consumption. Three dimensional (3D) stackable 1TnR (1 Transistor per “n” Resistive memory cells) or 1S1R (1 Selector per 1 Resistive memory cell) crossbar structures are necessary to achieve these density levels, and various selector devices, such as tunneling diodes, bidirectional varistors, and ovonic threshold switches, have been tested as solutions to the sneak path issue with only limited success.

Among the key requirements for a suitable selector are high selectivity (∆I @VR, 1/2VR), a steep turn-on slope, high current density, fast turn-on and recovery, and high endurance. Previous attempts at developing suitable selector devices have been reported with selectivity ranging from 150 to about 10^5, but circuit simulations have shown that a selectivity far larger than 10^5 is required to design megabit-level passive crossbar arrays.

Engineers at Crossbar, Inc., a start-up company developing 3D-stackable RRAM technology, have solved the sneak path problem with the development of the Field Assisted Superlinear Threshold (FAST) selector, a new design which has demonstrated the highest reported selectivity of 1010, as well as an extremely sharp turn-on slope of less than 5mV/dec, fast turn-on and recovery (< 50ns), an endurance greater than 100M cycles, and a processing temperature less than 300°C ensuring commercial viability. Measurements on a 4Mb 1S1R crossbar array with integrated FAST selectors show the sneak current suppressed to below 0.1nA, while maintaining a 102 memory on/off ratio and greater than 106 selectivity during cycling, making it ideal for ultra-high density memory applications.

The FAST Selector Device

The patented FAST selector device utilizes a superlinear threshold layer (STL), which forms a conduction path at the specified threshold voltage (VTH). The device provides extremely fast, bidirectional switching with a large resistance ratio, high turn-on current and steep turn-on slope, as shown in Figure 1a.

fig1a
Figure 1a. I-V characteristics of FAST selectors (100nm x 100nm). The device exhibits bidirectional threshold switching with an on/off ratio (test limited) greater than 107.

The measured selectivity for the 100nm x 100nm device is greater than 107 and limited by the test setup. The switching slope is extremely sharp – less than 5mV/dec. (Figure 1b), which is advantageous for array level operations (e.g. larger read voltage margin, faster read time).

fig1b
Figure 1b. Zoomed-in plot showing the extremely sharp FAST selector turn-on slope of less than 5mV/dec.
The threshold voltage (VTH) of the selector can be tuned by controlling either the STL thickness or the device structure (Figures 1c and 1d).
fig1c
Figure 1c. The threshold voltages can be tuned by controlling the SLT layer thickness.
fig1d
Figure 1d. Asymmetric threshold voltages can be achieved by controlling the device structure (by modulating the electric field).

The FAST selector can switch reliably for more than 100M cycles (test limited), and reliable switching can also be maintained in 15nm x 100nm devices, with current density greater than 5 x 106A/cm2. The FAST selector was DC stress tested at a constant 0.5VTH applied for two hours, and the device did not turn on, confirming good immunity to program/read disturb.

Switching speeds faster than 50ns can be achieved with voltages above VTH. The FAST selector can be turned on within 30ns. The off-to-on transition time is about 5ns (test limited) for over 300µA of passing current through the selector, and the device can quickly recover to the off state once the voltage is removed, with a recovery time of less than 50ns.

Once a FAST device switches to the on state, a target pass current, IP, can be delivered with a much smaller hold voltage, VH (Figure 2a). VH increases as IP increases, but it is independent of VTH (Figures 3b-d). The small VH (< 0.3V for 200µA) and very large off-state resistance minimize the voltage overhead when integrated with RRAM.

fig2
Figure 2. Hold voltage (VH) characteristics of FAST selectors. (a) Once a device switches on, a small VH is required for passing a specific target current (passing current IP). (b) IP vs. VH. (c) Median on resistances vs. IP. (d) VTH vs. VH.

Integrating FAST Selectors in Crossbar Arrays

The FAST selector has been successfully integrated into a 4Mb passive crossbar array, with a sneak current below 0.1nA at both 25°C and 125°C, demonstrating very high device yield and low leakage current.

For the integration, forming-free, low current (≤ 20µA) RRAM cells were developed to minimize IR drop and power consumption in large arrays (Figure 3a). FAST selectors with VTH larger than 0.5VPRG, but smaller than the VPRG of the RRAM, were designed to suppress sneak currents during both program and read operations (Figure 3b).

fig3
Figure 3. Passive crossbar integration of RRAM devices with FAST selectors. (a) I-V characteristics of a single cell level RRAM, (b) selector, and (c) integrated 1S1R device. (d) I-V characteristics of a 4Mb passive crossbar array based on 1S1R.

The resulting integrated 1S1R device exhibits a memory on/off ratio greater than 102 and selectivity greater than 106 (Figure 3c), and device operations have been successfully maintained for 4Mb 1S1R crossbar arrays (Figure 3d), which is the largest array size demonstrated to date for a passive crossbar structure.

The integrated 1S1R device switches reliably for more than 100K cycles while maintaining the large memory on/off ratio and selectivity (Figure 4).

fig4
Figure 4. Integrated 1S1R device cycling demonstration. On and off states and half-selected currents are shown. The integrated 1S1R device maintained > 102 memory on/off ratio and > 106 selectivity during the cycling.

When the leakage current through an entire 40Kb selector array was measured to extract the intrinsic leakage current of an individual selector (Figure 5a), the extracted selectivity was found to be 1010 (in a 100nm device). Figure 5a also shows that there is no single shorted selector device within the 40Kb selector array. The selectivity for different device areas was calculated using the same test method (Figure 5b). Circuit simulations show that a selectivity greater than 10^5 is required to design megabit-level passive crossbars, and the FAST selector clearly surpasses this requirement.

fig5
Figure 5. Leakage current test of selectors and the projected selectivity. (a) Leakage current through entire 40Kb devices and the projected 1-bit (100nm x 100nm) leakage current. Inset: Typical I-V of a selector on the same wafer. (b) The selectivity vs. device area based on the leakage current measurement.

Conclusion

The FAST selectors developed by Crossbar offer the largest reported selectivity to date (1010), as well as excellent performance metrics for other characteristics required for high density memory applications, including steep slope and fast turn on/recovery. The high selectivity of the FAST device, and its ability to be integrated directly into each RRAM memory cell, make it possible to move beyond the density limitations of 1T1R array structures and implement commercial memory products, based on 3D stackable 1TnR memory architectures, for ultra-high density nonvolatile memory application.

Share and Enjoy:
  • Digg
  • Sphinn
  • del.icio.us
  • Facebook
  • Mixx
  • Google
  • TwitThis
Extension Media websites place cookies on your device to give you the best user experience. By using our websites, you agree to placement of these cookies and to our Privacy Policy. Please click here to accept.