Industry Leading Tools Linking Simulation and ATPG to Test
Linking Simulation/ATPG to Test
Translating event-based simulation data (VCD and EVCD) to cycle-based ATE device testers can be complex and error-prone. Running under the Vtran User Interface (VUI), VTRAN, VCAP and DFTView provide a powerful set of tools to efficiently and flexibly accomplish this task. Simulation or ATPG files are automatically read, optionally have various conditioning and editing processes applied to them, and finally are cyclized and formatted for a target ATE. The resulting test programs can then be viewed graphically and optionally translated back into a Verilog or VHDL testbench for a validation simulation prior to being loaded onto the tester.
Powerful Vector Processing
VTRAN, VCAP and DFTView gives test engineers an unparalleled level of power and flexibility during the vector translation process – often a huge benefit when trying to get working test programs. Some of the key processing features include;
- Analysis of timing and waveforms in VCD/EVCD files
- Vector masking using numerous masking algorithms
- Adding new signals with state values a function of other signals
- Re-arranging signal ordering and name aliasing
- Inserting vector repeat functions and statement insertions
- Tracking of vector number, cycle number and scan bit counts
- Waveform viewing of STIL, WGL and VTRAN-generated ATE test programs
Visit us at www.sourceiii.com to access more information, review technical documents and download evaluation software to try it out for yourself. Source III’s technical support staff becomes an extension to your design and test groups to ensure your success. You get proven, reliable products with a full-time technical staff to support you. No other tools on the market can offer the level of scope, features, performance, support and cost that we offer. Learn more today!