New Innovative Chip Designs Mean Big Challenges for Chip Designers
The semiconductor industry is moving forward with new and innovative chip designs. Who couldn’t be impressed with the newest Apple products, newly emerging IoT applications, and the way in which large companies are moving into datacenter storage? With these bold moves, come big challenges for project teams.
Several challenges currently are vexing circuit designers. One of the most common is process variation and it will only become more pronounced as we hit the atomic level. With shrinking supply voltages, margins will be far less at the atomic dimension. It’s a complex and difficult problem, made only more so as designs become more robust.
Circuits are larger, margins are less at the atomic dimension and designers are looking for ways to squeeze performance and yield. One important consideration is accurate SPICE models that designers often request of the foundries.
However, model accuracy is subjective and depends highly on the application. Models are becoming complicated, as models must cover uncertainties of various process variations, including layout dependent systematic variations, statistical process variations, and temporal variations such as bias temperature instability (BTI)-induced reliability effects. Designers then need to look for statistical analysis and yield prediction software able to optimize parametrical yield and trade-off with power, performance and area (PPA) for this new challenge.
Reliability and yield are hard problems, especially as the margins left in the design are shrinking to almost zero. That means covering various process variation effects has become equally as important as modeling accuracy. Furthermore, yield needs to be considered across the whole system, considering various blocks have different contributions to yield based on their replication factor. It’s not enough just to look at the bit cell, but the whole critical path must be considered, including interactions across blocks. Getting it right has never been more significant. Modeling is a process in itself today as circuit designers break through the barriers and need better accuracy. Mask sets are more expensive and no company can afford a mistake. Designers are required to have a good understanding of the process platform, SPICE model libraries, and the impact to their designs, in order to achieve a good design and competitive chip products.
Designers are desperate as well for simulation and verification tools that will guarantee what they simulate is what they get. They’re simulating huge circuits now and the need to capture accurate leakage and other small currents is critical for low supply voltage applications. Correlation is a term that will be heard throughout this year and well into the future. For advanced low-power designs at 28nm and beyond, inaccurate simulation tools may predict leakage and other small currents wrongly with orders of magnitude differences. This easily will cause chip failure and waste time and the cost of tape-out. A typical example is to use a traditional FastSPICE tool, which sacrifies accuracy for performance, in verification and signoff of memory chips or embedded memory for large SoCs. Accuracy is the most critical of requirements throughout the entire design flow, in particular for characterization, post-layout simulation, verification and signoff.
These characteristics are some of the drivers for low power and more robust power supplies, an emerging area as we move into the more portable aspects of the Internet of Things.
Dr. Bruce McGaughy serves as the chief technology officer and senior vice president of Engineering of ProPlus Design Solutions, Inc. He was most recently the chief architect of Simulation Division and distinguished engineer at Cadence Design Systems Inc. Dr. McGaughy previously served as a R&D vice president at BTA Technology Inc. and Celestry Design Technology Inc., and later an engineering group director at Cadence Design Systems Inc. Dr. McGaughy holds a Ph.D. degree in EECS from the University of California at Berkeley.