2015 DAC Will Illuminate System Design Enablement Breakthroughs
By Brian Fuller, Cadence Design Systems
Each Design Automation Conference (DAC) brings with it its own themes, most driven by recent commercial or academic technology developments, others driven by public announcements. Five years ago, one of the major DAC themes was IP and EDA firmly joined at the hip. That was because Cadence had just acquired Denali and its memory and interface IP portfolio.
So what will be this year’s hot themes when the 52nd DAC convenes in the “cool, gray city of love,” San Francisco? To understand them, let’s step back briefly. Today, electronics design is driven by a handful of fundamental opportunities. Among them is the increasing proliferation of semiconductor content into existing markets (automotive and industrial come to mind). Electronic systems design also is being driven by markets that didn’t exist five years ago: wearables and Internet of Things (IoT), for example. And as these markets mature—almost all of them stitched together by various wireless protocols—security is a massive design concern.
These higher-level themes are reflected by some of this year’s event content and tracks, which you can find on the DAC site:
- Embedded systems
Dive deeper, and we confront a number of ever-present design challenges on the road to these opportunities. And these challenges are getting thornier as Moore’s Law passes its 50th birthday and process nodes dive below 10nm.
Here, like hot and cold fronts, opportunity and challenges collide. Take IoT: Design teams are under increasing pressure to design smaller, more power-efficient (or power-harvesting) devices at low cost points. That in and of itself is a massive challenge for global engineering teams. But because markets like IoT and automotive have so much potential, the competition has blossomed in the past 5-10 years. That raises another challenge: Missing a market window with the next product can be terminal.
WANTED: NEW THINKING
So enabling those system designs and conquering some of these challenges requires new thinking and new conversations in old areas—implementation, verification, debug, and IP use and integration.
Take IP for instance. Five years ago, that Cadence-Denali deal, struck a month before DAC, transformed how the industry viewed itself and how customers viewed EDA. “EDA,” as we know the industry, has been evolving ever since to position itself as an enabler of system designs. Let’s face it, with billions of transistors filling up SoCs that are using—on average—more than 120 IP blocks today, design teams need to focus on their design expertise and enlist help in areas around that expertise.
Much of this revolves around how to think about today’s systems and networks in the context of IoT. It’s not just about designing billions of transistors; it’s about designing for applications.
“It’s no longer possible to think of the system as just this chip or that chip,” said Chris Rowen, CTO of Cadence’s IP Group. “The system that we’re all dealing with is, in fact, my device, plus the wireless infrastructure, plus that Google cloud that together make up the environment of interest.”
He added that as we watch the data flow from data capture at the sensor level up through object tracking and augmented-reality application across an LTE network to an LTE base station, through the wired network to a data server with its SSD and HDD and reflecting off the far end and percolating that data back down, “You see just how interconnected it is.”
SYSTEM DESIGN SHIFTING LEFT
What used to be the leap from IP to EDA is no longer a leap in 2015 because so much of what teams are doing at the IP block is dictated by the end application. That requires a new way of delivering traditional EDA solutions. This year, the need to think at the system level, to do concurrent design—to understand and embrace the “shift left” in design—is front and center in San Francisco. One of the themes, then, that will resonate at this year’s DAC is smarter verification.
“Like our fridges and toasters in the IoT, advanced verification is becoming smarter,” said Frank Schirrmeister, group director for product marketing with Cadence’s System Development Suite. “Verification is shifting from a pure race on who can execute the most cycles fastest to how smart verification can be.”
Facing incredibly complex system and SoC designs, how do engineering teams determine the right engines to be used in the continuum of verification engines from TLM-based virtual prototyping to RTL-based simulation, acceleration, emulation, FPGA-based prototyping, and even the actual silicon?
Additional questions that need to be asked and answered include:
- How can designs move between engines smartly?
- How can the engines be smartly connected in hybrid fashions?
- How can post-silicon validation and pre-silicon verification interact smartly?
- How can my verification environment be re-used smartly across engines?
- How can debug become smarter than PRINTFs and instead focus on the roots of the defects?
“We’ll all go to school at DAC, and the current program already shows a plethora of activities in this area, ultimately showing us how to implement the ‘shift left’ everybody seems to be talking about,” Schirrmeister said.
Software is becoming even more important not only for its role in smart verification and ability to be re-used across engines but also as content to be verified. This is one driver behind a new addition to the program this year, the co-located Embedded TechCon.
Throughout DAC, attendees will hear discussions about how to efficiently debug hardware-software interactions with synchronized debug and which engines are the right ones for which part of the software? How can a user get to the point of interest fast and accelerate the boot up of operating systems?
Much of what’s driving today’s themes is a fundamental shift in design thinking in recent years. Gone are the days when IC vendors churned out chips and their customers stitched them together on a board and sprinkled some software on top. Today, application requirements drive IC design and tool developments.
“EDA has to understand what its customers are building and what their requirements are,” Schirrmeister said. “Be prepared for the discussions to extend well beyond the technical aspects, as the technologies we enable are changing how society behaves and interacts.”
So these are some of the high-level themes that are driving the opportunities and challenges that will echo through the halls of San Francisco’s Moscone Center in June as EDA and IP vendors mingle with systems and IC engineers.
For Cadence’s part, IP and EDA experts will converge on the 52nd DAC to shed light on most of these themes, from CEO Lip-Bu Tan’s fireside chat on Tuesday to an array of domain experts talking at nearly two-dozen different sessions, ranging from IoT to high-performance computing to design automation in the cloud to FPGAs and security to timing analysis and circuit simulation to signoff and more.
In addition to that and activities in and around the Cadence booth—including partner technical presentations in the theater and at Chip Estimate—Cadence is hosting one breakfast and three luncheons that offer up experts who will explore issues in mixed-signal design, next-generation verification, the move from 28nm to 16FF+ and leading-edge digital SoC design.
A complete roster of such sessions is available at www.cadence.com/dac2015.