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DAC Panel: Design Specialists Must Collaborate on Complex SoCs

Dr Fuller (125x125)

By Jeff Dorsch, Contributing Editor

A disgruntled designer of analog chips became the focal point of a Design Automation Conference panel session during lunchtime Wednesday.

The topic was “Methodology and Metrics for Analog/Mixed-Signal Verification: Madness or Marriage?” The panelists, all industry experts and veterans in their field, generally agreed that teamwork among analog and digital designers, verification specialists, and others was essential to the task of completing the design of a system-on-a-chip project.

Brian Fuller and Steve Lewis of Cadence Design Systems kicked off the session with a short skit. Lewis played the role of the disgruntled designer while his physician, “Dr. Fuller,” asked about what was going on with his SoC device project.

Lewis complained about how the “digital guys” were dominating the project and disrespecting his analog expertise. Dr. Fuller prescribed some anger-measurement measures and put on a latex glove, causing Lewis to uncomfortably back away and flee.

On a more serious note, Fuller introduced the three panelists: Andre Gunther of NXP Semiconductors, Neyaz Khan of Maxim Integrated Products, and Paul Magozzi of Semtech.

“Steve is a classic analog engineer,” Magozzi said, describing the skit character. In reality, people from different design specialties have to work together, he added.

“You’re not a silo,” Magozzi said of various IC designers. Team members have to actively collaborate and “hope it comes together at the top,” he noted.

Khan said it was necessary to “get everyone in a room” to discuss what’s needed in a design project. Khan said of Steve the character, “He should be open to talking to verification people.” He offered a maxim for successful design projects: “Plan, plan, plan.”

Gunther said, “I’m an analog designer by trade,” adding that the digital world is “taking a large piece of our life now.”

Even with elaborate planning and discussion, “we still make mistakes,” Gunther observed. “Unintended consequences happen.”

Even when using “golden IP,” trusted and useful intellectual property, things can still go wrong, he added. “You put it on a chip and poof, it fails.”

Gunther asserted, “Reuse is overuse.”

He continued, “I wouldn’t recommend buying critical IP; it has be handcrafted. PLL is kind of critical.

“I like to keep people like Steve happy,” Gunther said. “They need new views, new tools. I like to keep our brightest analog designers on analog design.”

Magozzi advised, “Sometimes you have to draw a hard line with people.”

Left to right: Paul Magozzi of Semtech, Neyaz Khan of Maxim Integrated Products, Andre Gunther of NXP Semiconductors, and Brian Fuller of Cadence Design Systems.

Left to right: Paul Magozzi of Semtech, Neyaz Khan of Maxim Integrated Products, Andre Gunther of NXP Semiconductors, and Brian Fuller of Cadence Design Systems.

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