The Quest for Low Power
Dave Bursky, Semiconductor Technology Editor
Lowering power consumption requires a holistic approach that touches every aspect of the design, from the transistors to the standard-cell building blocks, to the circuit architecture, and going all the way up to the application software running on the chip and system.
The tsunami of wearable and pocket-sized devices (cell phones, digital cameras, GPS devices, etc.), that run on batteries, as well as machine-to-machine (M2M) interfaces that can run from small amounts of energy, often harvested from the environment continues to put pressure on designers to craft circuits that consume smaller and smaller amounts of power. There are many approaches to lower circuit power consumption, and both technical presentation sessions and tools demonstrated by exhibitors at this week’s Design Automation Conference in San Francisco provided designers with great overview of design approaches and the tools available to help optimize the designs to reduce power consumption without degrading circuit performance.
At the transistor/process level, companies are hard at work shrinking process features down from the 22/20 nm regime to 16 nm and below, employing FinFET structures and yet-to-be-determined structures at 7 nm and beyond. Smaller transistors will consume less power, partially due to the smaller parasitic elements that reduce power losses, and partially from a reduced operating voltage. In sessions 1 and 2 of the Low Power IP program track, lluis Paris, the deputy director of IP portfolio marketing at Taiwan Semiconductor Manufacturing Co. (TSMC) detailed performance levels of various process nodes, from 55 nm down to 16 nm (Figure 1).
Basically, it shows that different processes are needed to cover both the high-performance and low-power requirements – one process can’t satisfy all the requirements. Thus TSMC developed a dedicated process for ultra-low-power applications. Some of the key blocks of intellectual property (IP) that would typically be implemented in the ULP process include real-time controllers which need ultra-low standby power consumption, SRAM cells with low-voltage data retention at levels as low at 0.2 V and low leakage currents due to the use of thick oxide layers that help reduce leakage currents, and embedded power management circuits that control power going to various functional blocks on the chip.
On the left side, the bar chart in Figure 1 shows how low the Vdd supply level can go at each process node for its low-power and ultra-low-power process options. The bar chart on the upper right side of the image shows the variation in transistor threshold voltage (Vt) for the same process options, while the chart on the lower right shows the leakage current differences for an SRAM bit cell for the same process options and feature sizes. To meet the designer’s needs Paris stated that the tools have to be improved – for near-threshold and sub-threshold designs, Spice modelling must get better and library characterization must be improve for near-threshold operation by tightening margins, reducing cell area, and lowering power consumption.
Power Management Options Lead to Tradeoffs
In addition to improving the operating margins for individual cells, various power-management schemes such as clock gating and power gating can go a long way to lowering chip power by stopping the clock to circuit blocks that idle, or actually shutting off the power going to circuit blocks that aren’t needed at the moment. However with each of these approaches, the circuit performance can suffer from latencies caused by the restart sequence of the various blocks to go from idle or off to full operation. Dr. Drew Wingard, the CTO and cofounder of Sonics, in his presentation in Session 1 assembled a table that examines several functions that are often targets for clock or power gating, and the restart latencies that each block would impose on circuit performance (Table 1). In some cases, such as fine-grained clock gating or coarse-grained clock gating, the penalty is just 1 or 2 clock cycles (a few nanoseconds). However more complex power-savings schemes such as power switching and adaptive voltage and frequency scaling can cost a system 5-30 microseconds for power switching, and from 0.4 to 1.5 milliseconds for adapting voltage/frequency scaling.
These latencies must be accounted for when designing the chip. In some cases, the chip performance could take a significant hit and that could obviate the benefits of the power reduction techniques. Basically, Dr. Wingard provided some words of advice as to have the design should proceed – identify regions of an SoC that will be idle, partition the design to isolate similar regions and select the appropriate power savings techniques, determine idle and activating conditions, and control the power-state transitions to ensure chip performance and safe operation.
Another issue when doing a low-power SoC design – internal IR drops on the power delivery paths to IP blocks on the chip. This problem escalates at low-voltage operation, as Aditya Mukherjee, the director of hardware engineering, silicon development team at Microsoft Corp., pointed out in Session 1. Since the voltage is already low, any IR drop on the internal metal paths will further reduce the operating voltage, possibly to a level below the transistor threshold, thus causing unstable circuit operation. To deal with this during the design of an imaging chip, RTL-level power analysis was done using the Ansys PowerArtist took and the results correlated to silicon. RTL power regression analysis was then done over a large number of full chip tests to identify the worst power state and idle time windows.
Although a lot of attention has been paid to reducing the power on digital circuits as transistors scale, there is also a large challenge looming for analog circuit power reduction as designers try to leverage 16 nm FinFET devices to build mixed-signal circuits on the same chip that has lots of digital IP. Enhanced tools from Synopsys are taking on that challenge according to Fred Sendig, Manager of the Analog and Mixed Signal Tools group. Tools have to deal with many device and circuit level issues – resistance, electromigration, IR voltage drops, and parasitic capacitance to name a few. Additionally, FinFET based analog circuits are especially sensitive to physical layout issues, especially if device matching is important. In fact, creating a matched pair requires creating placement array patterns comprising dozens to hundreds of FinFET devices and averaging the performance of the array to achieve the desired result.
Over the last three days, the many sessions and exhibitors at DAC touched on multiple low-power design issues and solutions . On the show floor, innovative IP blocks and tools will help come to the designer’s rescue. For instance, Surecore’s CEO, Paul Wells, introduced an ultra-low-power SRAM memory cell that can be implemented in either FDSOI (fully depleted silicon on insulator), or bulk silicon. When implemented in a 28-nm FDSOI process, a 2kword x 72-bit memory array when operating at 1 V and 25 degrees C, has just 4 microwatts of leakage power, an access time of 0.67 ns, a cycle time of 0.77 ns, and dynamic read and write power consumptions of 6.9 and 6.2 microwatts/megahertz, respectively. For more information about presentations at DAC, and a full exhibitor’s list, go to www.dac.com.